SN54LV594A Search Results

A115-A

Abstract: C101 SN54LV594A SN74LV594A
Contextual Info: SN54LV594A, SN74LV594A 8-BIT SHIFT REGISTERS WITH OUTPUT REGISTERS SCLS413E – APRIL 1998 – REVISED OCTOBER 2002 D D D D 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC QA SER RCLR RCLK SRCLK SRCLR QH′ SN54LV594A . . . FK PACKAGE TOP VIEW QD QE NC QF QG 3 2 1 20 19

Contextual Info: SN54LV594A, SN74LV594A 8-BIT SHIFT REGISTERS WITH OUTPUT REGISTERS SCLS413F – APRIL 1998 – REVISED AUGUST 2003 D D D D 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC QA SER RCLR RCLK SRCLK SRCLR QH′ SN54LV594A . . . FK PACKAGE TOP VIEW QD QE NC QF QG 3 2 1 20 19

Contextual Info: SN54LV594A, SN74LV594A 8ĆBIT SHIFT REGISTERS WITH OUTPUT REGISTERS SCLS413I − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 6.5 ns at 5 V D Typical VOLP Output Ground Bounce D D D 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC QA SER

A115-A

Abstract: C101 SN54LV594A SN74LV594A SN74LV594AD
Contextual Info: SN54LV594A, SN74LV594A 8ĆBIT SHIFT REGISTERS WITH OUTPUT REGISTERS SCLS413I − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 6.5 ns at 5 V D Typical VOLP Output Ground Bounce D D D 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC QA SER

Contextual Info: SN54LV594A, SN74LV594A 8ĆBIT SHIFT REGISTERS WITH OUTPUT REGISTERS SCLS413I − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 6.5 ns at 5 V D Typical VOLP Output Ground Bounce D D D 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC QA SER

LV594A

Abstract: 74LV594 A115-A C101 SN54LV594A SN74LV594A SN74LV594AD
Contextual Info: SN54LV594A, SN74LV594A 8ĆBIT SHIFT REGISTERS WITH OUTPUT REGISTERS SCLS413G − APRIL 1998 − REVISED SEPTEMBER 2003 D 2-V to 5.5-V VCC Operation D Max tpd of 6.5 ns at 5 V D Typical VOLP Output Ground Bounce D D D 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC QA

A115-A

Abstract: C101 SN54LV594A SN74LV594A SN74LV594AD LV594A
Contextual Info: SN54LV594A, SN74LV594A 8ĆBIT SHIFT REGISTERS WITH OUTPUT REGISTERS SCLS413I − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 6.5 ns at 5 V D Typical VOLP Output Ground Bounce D D D 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC QA SER

Contextual Info: SN54LV594A, SN74LV594A 8-BIT SHIFT REGISTERS WITH OUTPUT REGISTERS SCLS413C – APRIL 1998 – REVISED MAY 2000 D D D D D 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC QA SER RCLR RCLK SRCLK SRCLR QH′ SN54LV594A . . . FK PACKAGE TOP VIEW QD QE NC QF QG 4 3 2 1 20 19

Contextual Info: SN54LV594A, SN74LV594A 8-BIT SHIFT REGISTERS WITH OUTPUT REGISTERS SCLS413C – APRIL 1998 – REVISED MAY 2000 D D D D D 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC QA SER RCLR RCLK SRCLK SRCLR QH′ SN54LV594A . . . FK PACKAGE TOP VIEW QD QE NC QF QG 4 3 2 1 20 19

Contextual Info: SN54LV594A, SN74LV594A 8ĆBIT SHIFT REGISTERS WITH OUTPUT REGISTERS SCLS413I − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 6.5 ns at 5 V D Typical VOLP Output Ground Bounce D D D 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC QA SER

Contextual Info: SN54LV594A, SN74LV594A 8ĆBIT SHIFT REGISTERS WITH OUTPUT REGISTERS SCLS413I − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 6.5 ns at 5 V D Typical VOLP Output Ground Bounce D D D 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC QA SER

A115-A

Abstract: C101 SN54LV594A SN74LV594A SN74LV594AD
Contextual Info: SN54LV594A, SN74LV594A 8ĆBIT SHIFT REGISTERS WITH OUTPUT REGISTERS SCLS413H − APRIL 1998 − REVISED DECEMBER 2004 D 2-V to 5.5-V VCC Operation D Max tpd of 6.5 ns at 5 V D Typical VOLP Output Ground Bounce D D D 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC QA

Contextual Info: SN54LV594A, SN74LV594A 8-BIT SHIFT REGISTERS WITH OUTPUT REGISTERS SCLS413A – APRIL 1998 – JUNE 1998 D description The ’LV594A devices are 8-bit shift registers designed for 2-V to 5.5-V VCC operation. These devices contain an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type

Contextual Info: SN54LV594A, SN74LV594A 8ĆBIT SHIFT REGISTERS WITH OUTPUT REGISTERS SCLS413I − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 6.5 ns at 5 V D Typical VOLP Output Ground Bounce D D D 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC QA SER

A115-A

Abstract: C101 SN54LV594A SN74LV594A
Contextual Info: SN54LV594A, SN74LV594A 8-BIT SHIFT REGISTERS WITH OUTPUT REGISTERS SCLS413C – APRIL 1998 – REVISED MAY 2000 D D D D D 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC QA SER RCLR RCLK SRCLK SRCLR QH′ SN54LV594A . . . FK PACKAGE TOP VIEW QD QE NC QF QG 4 3 2 1 20 19

A115-A

Abstract: C101 SN54LV594A SN74LV594A SN74LV594AD
Contextual Info: SN54LV594A, SN74LV594A 8ĆBIT SHIFT REGISTERS WITH OUTPUT REGISTERS SCLS413H − APRIL 1998 − REVISED DECEMBER 2004 D 2-V to 5.5-V VCC Operation D Max tpd of 6.5 ns at 5 V D Typical VOLP Output Ground Bounce D D D 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC QA

Contextual Info: SN54LV594A, SN74LV594A 8ĆBIT SHIFT REGISTERS WITH OUTPUT REGISTERS SCLS413I − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 6.5 ns at 5 V D Typical VOLP Output Ground Bounce D D D 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC QA SER

610110

Abstract: A115-A C101 SN54LV594A SN74LV594A
Contextual Info: SN54LV594A, SN74LV594A 8-BIT SHIFT REGISTERS WITH OUTPUT REGISTERS SCLS413D – APRIL 1998 – REVISED JANUARY 2001 D D D D description 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC QA SER RCLR RCLK SRCLK SRCLR QH′ SN54LV594A . . . FK PACKAGE TOP VIEW QD QE

A115-A

Abstract: C101 SN54LV594A SN74LV594A SN74LV594AD
Contextual Info: SN54LV594A, SN74LV594A 8ĆBIT SHIFT REGISTERS WITH OUTPUT REGISTERS SCLS413I − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 6.5 ns at 5 V D Typical VOLP Output Ground Bounce D D D 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC QA SER

A115-A

Abstract: C101 SN54LV594A SN74LV594A
Contextual Info: SN54LV594A, SN74LV594A 8-BIT SHIFT REGISTERS WITH OUTPUT REGISTERS SCLS413D – APRIL 1998 – REVISED JANUARY 2001 D D D D description 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC QA SER RCLR RCLK SRCLK SRCLR QH′ SN54LV594A . . . FK PACKAGE TOP VIEW QD QE

Contextual Info: SN54LV594A, SN74LV594A 8ĆBIT SHIFT REGISTERS WITH OUTPUT REGISTERS SCLS413I − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 6.5 ns at 5 V D Typical VOLP Output Ground Bounce D D D 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC QA SER

Contextual Info: SN54LV594A, SN74LV594A 8ĆBIT SHIFT REGISTERS WITH OUTPUT REGISTERS SCLS413I − APRIL 1998 − REVISED APRIL 2005 SN54LV594A . . . J OR W PACKAGE SN74LV594A . . . D, DB, NS, OR PW PACKAGE TOP VIEW D 2-V to 5.5-V VCC Operation D Max tpd of 6.5 ns at 5 V

Contextual Info: SN54LV594A, SN74LV594A 8ĆBIT SHIFT REGISTERS WITH OUTPUT REGISTERS SCLS413I − APRIL 1998 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 6.5 ns at 5 V D Typical VOLP Output Ground Bounce D D D 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC QA SER

Contextual Info: SN54LV594A, SN74LV594A 8-BIT SHIFT REGISTERS WITH OUTPUT REGISTERS S C L S 4 1 3 A -A P R IL 1998 - JU N E 1998 EPIC Enhanced-Performance Implanted CMOS Process SN54LV594A . . . J OR W PACKAGE SN74LV594A . . . D, DB, DGV, NS, OR PW PACKAGE (TOP VIEW)