SN54LV32 Search Results

Contextual Info: SN54LV32, SN74LV32 QUADRUPLE 2-INPUT POSITIVE-OR GATES SCLS188C – FEBRUARY 1993 – REVISED APRIL 1996 D D D D D EPIC  Enhanced-Performance Implanted CMOS 2-µ Process Typical VOLP (Output Ground Bounce) < 0.8 V at VCC, TA = 25°C Typical VOHV (Output VOH Undershoot)

Contextual Info: SN54LV32, SN74LV32 QUADRUPLE 2ĆINPUT POSITIVEĆOR GATES SCLS188C − FEBRUARY 1993 − REVISED APRIL 1996 D EPIC  Enhanced-Performance Implanted D D D D CMOS 2-µ Process Typical VOLP (Output Ground Bounce) < 0.8 V at VCC, TA = 25°C Typical VOHV (Output VOH Undershoot)

SN54LV32A

Abstract: SN74LV32A
Contextual Info: SN54LV32A, SN74LV32A QUADRUPLE 2-INPUT POSITIVE-OR GATES SCLS385C – SEPTEMBER 1997 – REVISED MAY 2000 D D D D D D D EPIC  Enhanced-Performance Implanted CMOS Process Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot)

Contextual Info: SN54LV32, SN74LV32 QUADRUPLE 2ĆINPUT POSITIVEĆOR GATES SCLS188C − FEBRUARY 1993 − REVISED APRIL 1996 SN54LV32 . . . J OR W PACKAGE SN74LV32 . . . D, DB, OR PW PACKAGE TOP VIEW D EPIC  (Enhanced-Performance Implanted D D D D 1A 1B 1Y 2A 2B 2Y GND

Contextual Info: SN54LV32A, SN74LV32A QUADRUPLE 2-INPUT POSITIVE-OR GATES SCLS385J − SEPTEMBER 1997 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 6.5 ns at 5 V D Typical VOLP Output Ground Bounce D <0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot)

LV32A

Contextual Info: SN54LV32A, SN74LV32A QUADRUPLE 2-INPUT POSITIVE-OR GATES SCLS385E – SEPTEMBER 1997 – REVISED AUGUST 2002 SN54LV32A . . . J OR W PACKAGE SN74LV32A . . . D, DB, DGV, NS, OR PW PACKAGE TOP VIEW 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4B 4A 4Y 3B 3A 3Y 1B 1Y

A115-A

Abstract: C101 SN54LV32A SN74LV32A
Contextual Info: SN54LV32A, SN74LV32A QUADRUPLE 2ĆINPUT POSITIVEĆOR GATES SCLS385J − SEPTEMBER 1997 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 6.5 ns at 5 V D Typical VOLP Output Ground Bounce D <0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot)

Contextual Info: SN54LV32A, SN74LV32A QUADRUPLE 2ĆINPUT POSITIVEĆOR GATES SCLS385J − SEPTEMBER 1997 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 6.5 ns at 5 V D Typical VOLP Output Ground Bounce D <0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot)

Contextual Info: SN54LV32A, SN74LV32A QUADRUPLE 2-INPUT POSITIVE-OR GATES SCLS385G – SEPTEMBER 1997 – REVISED OCTOBER 2002 SN54LV32A . . . J OR W PACKAGE SN74LV32A . . . D, DB, DGV, NS, OR PW PACKAGE TOP VIEW 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4B 4A 4Y 3B 3A 3Y 1B 1Y

Contextual Info: SN54LV32A, SN74LV32A QUADRUPLE 2-INPUT POSITIVE-OR GATES SCLS385J − SEPTEMBER 1997 − REVISED APRIL 2005 D Ioff Supports Partial-Power-Down Mode D 2-V to 5.5-V VCC Operation D Max tpd of 6.5 ns at 5 V D Typical VOLP Output Ground Bounce 2 13 3 12 4 11

A115-A

Abstract: C101 SN54LV32A SN74LV32A 74LV32a
Contextual Info: SN54LV32A, SN74LV32A QUADRUPLE 2ĆINPUT POSITIVEĆOR GATES SCLS385J − SEPTEMBER 1997 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 6.5 ns at 5 V D Typical VOLP Output Ground Bounce D <0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot)

A115-A

Abstract: C101 SN54LV32A SN74LV32A
Contextual Info: SN54LV32A, SN74LV32A QUADRUPLE 2ĆINPUT POSITIVEĆOR GATES SCLS385J − SEPTEMBER 1997 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 6.5 ns at 5 V D Typical VOLP Output Ground Bounce D <0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot)

A115-A

Abstract: C101 SN54LV32A SN74LV32A 74LV32A
Contextual Info: SN54LV32A, SN74LV32A QUADRUPLE 2-INPUT POSITIVE-OR GATES SCLS385D – SEPTEMBER 1997 – REVISED JANUARY 2001 D D D D SN54LV32A . . . J OR W PACKAGE SN74LV32A . . . D, DB, DGV, NS, OR PW PACKAGE TOP VIEW 2-V to 5.5-V VCC Operation Typical VOLP (Output Ground Bounce)

Contextual Info: SN54LV32A, SN74LV32A QUADRUPLE 2-INPUT POSITIVE-OR GATES S C L S 3 8 5 A - S E P TE M B E R 1997 - R EVISED A P R IL 1998 EP/C Enhanced-Performance Implanted CMOS Process SN54LV32A . . . J OR W PACKAGE SN74LV32A . . . D, DB, DGV, NS, OR PW PACKAGE (TOP VIEW)

LV32

Abstract: SN54LV32 SN74LV32
Contextual Info: SN54LV32, SN74LV32 QUADRUPLE 2-INPUT POSITIVE-OR GATES SCLS188C – FEBRUARY 1993 – REVISED APRIL 1996 D D D D D EPIC  Enhanced-Performance Implanted CMOS 2-µ Process Typical VOLP (Output Ground Bounce) < 0.8 V at VCC, TA = 25°C Typical VOHV (Output VOH Undershoot)

A115-A

Abstract: C101 SN54LV32A SN74LV32A
Contextual Info: SN54LV32A, SN74LV32A QUADRUPLE 2ĆINPUT POSITIVEĆOR GATES SCLS385J − SEPTEMBER 1997 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 6.5 ns at 5 V D Typical VOLP Output Ground Bounce D <0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot)

SN54LV32A

Abstract: SN74LV32A
Contextual Info: SN54LV32A, SN74LV32A QUADRUPLE 2-INPUT POSITIVE-OR GATES SCLS385B – SEPTEMBER 1997 – REVISED NOVEMBER 1999 D D D D D EPIC Enhanced-Performance Implanted CMOS Process Typical VOLP (Output Ground Bounce) < 0.8 V at VCC, TA = 25°C Typical VOHV (Output VOH Undershoot)

Contextual Info: SN54LV32A, SN74LV32A QUADRUPLE 2-INPUT POSITIVE-OR GATES SCLS385G – SEPTEMBER 1997 – REVISED OCTOBER 2002 SN54LV32A . . . J OR W PACKAGE SN74LV32A . . . D, DB, DGV, NS, OR PW PACKAGE TOP VIEW 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4B 4A 4Y 3B 3A 3Y 1B 1Y

LV32A

Abstract: 74LV32A A115-A C101 SN54LV32A SN74LV32A
Contextual Info: SN54LV32A, SN74LV32A QUADRUPLE 2-INPUT POSITIVE-OR GATES SCLS385D – SEPTEMBER 1997 – REVISED JANUARY 2001 D D D D SN54LV32A . . . J OR W PACKAGE SN74LV32A . . . D, DB, DGV, NS, OR PW PACKAGE TOP VIEW 2-V to 5.5-V VCC Operation Typical VOLP (Output Ground Bounce)

Contextual Info: SN54LV32, SN74LV32 QUADRUPLE 2ĆINPUT POSITIVEĆOR GATES SCLS188C − FEBRUARY 1993 − REVISED APRIL 1996 D EPIC  Enhanced-Performance Implanted D D D D CMOS 2-µ Process Typical VOLP (Output Ground Bounce) < 0.8 V at VCC, TA = 25°C Typical VOHV (Output VOH Undershoot)

A115-A

Abstract: C101 SN54LV32A SN74LV32A
Contextual Info: SN54LV32A, SN74LV32A QUADRUPLE 2ĆINPUT POSITIVEĆOR GATES SCLS385I − SEPTEMBER 1997 − REVISED DECEMBER 2004 D 2-V to 5.5-V VCC Operation D Max tpd of 6.5 ns at 5 V D Typical VOLP Output Ground Bounce D <0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot)

Contextual Info: SN54LV32, SN74LV32 QUADRUPLE 2ĆINPUT POSITIVEĆOR GATES SCLS188C − FEBRUARY 1993 − REVISED APRIL 1996 D EPIC  Enhanced-Performance Implanted D D D D CMOS 2-µ Process Typical VOLP (Output Ground Bounce) < 0.8 V at VCC, TA = 25°C Typical VOHV (Output VOH Undershoot)

Contextual Info: SN54LV32A, SN74LV32A QUADRUPLE 2ĆINPUT POSITIVEĆOR GATES SCLS385J − SEPTEMBER 1997 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 6.5 ns at 5 V D Typical VOLP Output Ground Bounce D <0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot)

A115-A

Abstract: C101 SN54LV32A SN74LV32A
Contextual Info: SN54LV32A, SN74LV32A QUADRUPLE 2-INPUT POSITIVE-OR GATES SCLS385G – SEPTEMBER 1997 – REVISED OCTOBER 2002 SN54LV32A . . . J OR W PACKAGE SN74LV32A . . . D, DB, DGV, NS, OR PW PACKAGE TOP VIEW 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4B 4A 4Y 3B 3A 3Y 1B 1Y