SN54AC Search Results

Contextual Info: SN54AC74, SN74AC74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET _SCASS21C- AUGUST 199S - REVISED SEPTEMBER 1996 EPIC Enhanced-Performance Implanted CMOS 1-|im Process SN54AC74 . . . J OR W PACKAGE SN74AC74 . . . D, DB, N, OR PW PACKAGE

SN74ACTOO

Contextual Info: SN54ACT00, SN74ACT00 QUADRUPLE 2-INPUT POSITIVE-NAND GATES S C A S 5 2 3 A -AU G U S T 199S - R E V IS E D MAY 1996 Inputs Are TTL-Voltage Compatible EPIC Enhanced-Performance Implanted CMOS 1-ixm Process Package Options Include Plastic Small-Outllne (D), Shrink Small-Outllne

Contextual Info: SN54ACT3641 1024 x 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY SGBS309A - AUGUST 1995 - REVISED APRIL 1998 • Free-Running CLKA and CLKB Can Be Asynchronous or Coincident • Output-Ready and Almost-Empty Flags Synchronized by CLKB • Clocked FIFO Buffering Data From Port A

Contextual Info: SN54AC534, SN74AC534 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS SCAS554A – NOVEMBER 1995 – REVISED MAY 1996 D D D SN54AC534 . . . J OR W PACKAGE SN74AC534 . . . DB, DW, N, OR PW PACKAGE TOP VIEW 3-State Inverting Outputs Drive Bus Lines

SN54AC04

Contextual Info: SN54AC04, SN74AC04 HEX INVERTERS SCAS519C – JULY 1995 – REVISED SEPTEMBER 1996 D D EPIC  Enhanced-Performance Implanted CMOS 1-µm Process Package Options Include Plastic Small-Outline (D), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW)

Contextual Info: SN54AC240, SN74AC240 OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCAS512C – JUNE 1995 – REVISED SEPTEMBER 1996 D EPIC  Enhanced-Performance Implanted CMOS 1-µm Process Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), Thin Shrink Small-Outline (PW), and

Contextual Info: SN54AC08, SN74AC08 QUADRUPLE 2-INPUT POSITIVE-AND GATES SCAS536B – SEPTEMBER 1995 – REVISED SEPTEMBER 1996 D EPIC  Enhanced-Performance Implanted CMOS 1-µm Process Package Options Include Plastic Small-Outline (D), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW)

Contextual Info: SN54AC32, SN74AC32 QUADRUPLE 2-INPUT POSITIVE-OR GATES SCAS528B – AUGUST 1995 – REVISED SEPTEMBER 1996 D EPIC  Enhanced-Performance Implanted CMOS 1-µm Process Package Options Include Plastic Small-Outline (D), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW)

Contextual Info: SN54ACT563, SN74ACT563 OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS SCAS550A – NOVEMBER 1995 – REVISED 1996 D D D SN54ACT563 . . . J OR W PACKAGE SN74ACT563 . . . DB, DW, N, OR PW PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible 3-State Inverted Outputs Drive Bus Lines

Contextual Info: SN54AC240, SN74AC240 OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCAS512C – JUNE 1995 – REVISED SEPTEMBER 1996 D EPIC  Enhanced-Performance Implanted CMOS 1-µm Process Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), Thin Shrink Small-Outline (PW), and

Contextual Info: SN54ACT00, SN74ACT00 QUADRUPLE 2-INPUT POSITIVE-NAND GATES SCAS523B – AUGUST 1995 – REVISED AUGUST 1999 D D D SN54ACT00 . . . J OR W PACKAGE SN74ACT00 . . . D, DB, N, OR PW PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible EPIC  (Enhanced-Performance Implanted

SN54AC04

Contextual Info: SN54AC04, SN74AC04 HEX INVERTERS SCAS519C – JULY 1995 – REVISED SEPTEMBER 1996 D D EPIC  Enhanced-Performance Implanted CMOS 1-µm Process Package Options Include Plastic Small-Outline (D), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW)

Contextual Info: SN54ACT3641 1024 x 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY SGBS309A – AUGUST 1995 – REVISED APRIL 1998 D D D D D D D D Free-Running CLKA and CLKB Can Be Asynchronous or Coincident Clocked FIFO Buffering Data From Port A to Port B Memory Size: 1024 × 36

Contextual Info: SN54ACT14, SN74ACT14 HEX SCHMITT-TRIGGER INVERTER SCAS557D – DECEMBER 1995 – REVISED MARCH 1998 D D D Inputs Are TTL-Voltage Compatible EPIC  Enhanced-Performance Implanted CMOS 1-µm Process Package Options Include Plastic Small-Outline (D), Shrink Small-Outline

Contextual Info: SN54AC240, SN74AC240 OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCAS512C – JUNE 1995 – REVISED SEPTEMBER 1996 D EPIC  Enhanced-Performance Implanted CMOS 1-µm Process Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), Thin Shrink Small-Outline (PW), and

Contextual Info: SN54ACT00, SN74ACT00 QUADRUPLE 2-INPUT POSITIVE-NAND GATES SCAS523B – AUGUST 1995 – REVISED AUGUST 1999 D D D SN54ACT00 . . . J OR W PACKAGE SN74ACT00 . . . D, DB, N, OR PW PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible EPIC  (Enhanced-Performance Implanted

Contextual Info: SN54AC02-DIE www.ti.com SCHS392 – MAY 2013 RAD-TOLERANT, QUADRUPLE 2-INPUT POSITIVE-NOR GATES Check for Samples: SN54AC02-DIE FEATURES 1 • • 1 AC Types Feature 1.5-V to 5.5-V Operation Rad-Tolerant: 50 KRad(Si) TID (1) – TID Dose Rate < 2 mRad/sec

Contextual Info: SN54AC11, SN74AC11 TRIPLE 3ĆINPUT POSITIVEĆAND GATES SCAS532D − AUGUST 1995 − REVISED OCTOBER 2003 D 2-V to 6-V VCC Operation D Inputs Accept Voltages to 6 V D Max tpd of 7.5 ns at 5 V 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 1C 1Y 3A 3B 3C 3Y 2A NC 2B NC

Contextual Info: SN54AC11, SN74AC11 TRIPLE 3ĆINPUT POSITIVEĆAND GATES SCAS532D − AUGUST 1995 − REVISED OCTOBER 2003 D 2-V to 6-V VCC Operation D Inputs Accept Voltages to 6 V D Max tpd of 7.5 ns at 5 V 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 1C 1Y 3A 3B 3C 3Y 2A NC 2B NC

SN54AC86

Abstract: SN74AC86 SN74AC86D SN74AC86DBR SN74AC86DR SN74AC86N SN74AC86NSR SN74AC86PW SN74AC86PWR
Contextual Info: SN54AC86, SN74AC86 QUADRUPLE 2ĆINPUT EXCLUSIVEĆOR GATES SCAS533C − AUGUST 1995 − REVISED OCTOBER 2003 D 2-V to 6-V VCC Operation D Inputs Accept Voltages to 6 V D Max tpd of 9 ns at 5 V SN54AC86 . . . FK PACKAGE TOP VIEW 1A 1B 1Y 2A 2B 2Y GND 1 14

SN54AC00

Abstract: SN74AC00 SN74AC00D SN74AC00DBR SN74AC00DR SN74AC00N SN74AC00NSR SN74AC00PW SN74AC00PWR 5962-87549012A
Contextual Info: SN54AC00, SN74AC00 QUADRUPLE 2ĆINPUT POSITIVEĆNAND GATES SCAS524E − AUGUST 1995 − REVISED OCTOBER 2003 D 2-V to 6-V VCC Operation D Inputs Accept Voltages to 6 V D Max tpd of 7 ns at 5 V SN54AC00 . . . FK PACKAGE TOP VIEW 1 14 2 13 3 12 4 11 5 10 6

AC374

Abstract: SN54AC374 SN74AC374 SN74AC374DBR SN74AC374DW SN74AC374DWR SN74AC374N SN74AC374NSR SN74AC374PW
Contextual Info: SN54AC374, SN74AC374 OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS SCAS543E − OCTOBER 1995 - REVISED OCTOBER 2003 D SN54AC374 . . . J OR W PACKAGE SN74AC374 . . . DB, DW, N, NS, OR PW PACKAGE TOP VIEW 2-V to 6-V VCC Operation Inputs Accept Voltages to 6 V

AD374

Abstract: ACT374 SN54ACT374 SN74ACT374 SN74ACT374DBR SN74ACT374DW SN74ACT374DWR SN74ACT374N SN74ACT374NSR SN74ACT374PWR
Contextual Info: SN54ACT374, SN74ACT374 OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS SCAS539F − OCTOBER 1995 − REVISED NOVEMBER 2002 SN54ACT374 . . . J OR W PACKAGE SN74ACT374 . . . DB, DW, N, NS, OR PW PACKAGE TOP VIEW 4.5-V to 5.5-V VCC Operation Inputs Accept Voltages to 5.5 V

SN54ACT245

Abstract: SN74ACT245 SN74ACT245DBR SN74ACT245DW SN74ACT245DWR SN74ACT245N SN74ACT245NSR SN74ACT245PWR SNJ54ACT245J SN74ACT245PWLE
Contextual Info: SN54ACT245, SN74ACT245 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCAS452E – SEPTEMBER 1994 – REVISED OCTOBER 2002 D D 4.5-V to 5.5-V VCC Operation Inputs Accept Voltages to 5.5 V Max tpd of 8 ns at 5 V Inputs Are TTL-Voltage Compatible SN54ACT245 . . . J OR W PACKAGE