SMD ARAY Search Results

Contextual Info: ADS8381EVM User’s Guide September 2004 Data Acquistion SLAU133A IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries TI reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue

ADS8381EVM

Abstract: aray resistor smd g2a TMS320C5000 ADS8381 REF3020 REF3040 SN74AHC138 SN74AHC1G04 SN74AHC245
Contextual Info: ADS8381EVM User’s Guide May 2004 Data Acquistion SLAU133 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries TI reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue

TAIYO YUDEN LEM

Contextual Info: «Hÿfc - Æ COMPONENTS FOR HIGH FREQUENCY/MOBILE COMMUNICATION EQUIPMENT 20 TAIYO YUDEN Applied Circuit Block P/N Series Case Size nm Appearance UG Available Range/ Application Page 6 .2 X 6 .2 X 1 .9 ~ 7 .0 X 7 .0 X 2 .0

resistor cross reference

Abstract: 503-0 Vitrohm 502 Vitrohm Phycomp 232270591001 power 4532M BC Z5U 1KV Phycom 23227046 Phycom RC22H 232270492007 10K 471
Contextual Info: Innovative Service Around the Globe Chip Capacitors www.yageo.com Chip Resistors + HF Products www.yageo.com GENERAL INFORMATION Part numbering system and ordering You can order components from this catalogue in two ways. Both ways give logistic and packing

RTSX32SU

Abstract: RTSX32SU CQ84 rtsx72su RTSX32 RTSX-SU 1/RTSX32su CC256 PRB-1 actel 1020 datasheet CG624
Contextual Info: Revision 7 RTSX-SU RadTolerant FPGAs UMC FuseLock Designed for Space • • • • • SEU-Hardened Registers Eliminate the Need to Implement Triple-Module Redundancy (TMR) – Immune to Single-Event Upsets (SEU) to LETth > 40 MeV-cm2/mg, – SEU Rate < 10–10 Upset/Bit-Day in Worst-Case

RTSX32SU CQ84 PROTO

Abstract: CQ84 SOC 8A fuse smd RTSX32SU CQ84 rtsx72su RTSX32SU CG624 thermal expansion
Contextual Info: Revision 8 RTSX-SU Radiation-Tolerant FPGAs UMC Designed for Space • SEU-Hardened Registers Eliminate the Need to Implement Triple-Module Redundancy (TMR) – Immune to Single Event Upsets (SEU) to LETth > 40 MeVcm2/mg, – SEU Rate < 10–10 Upset/Bit-Day in Worst-Case

RTSX32SU CQ84 PROTO

Abstract: RTSX32SU CQ84 RTSX72SU1 SOC 8A fuse smd RTSX32su CG624 thermal expansion
Contextual Info: Revision 9 RTSX-SU Radiation-Tolerant FPGAs UMC Designed for Space • SEU-Hardened Registers Eliminate the Need to Implement Triple-Module Redundancy (TMR) – Immune to Single Event Upsets (SEU) to LETth > 40 MeVcm2/mg, – SEU Rate < 10–10 Upset/Bit-Day in Worst-Case

SMD ARAY

Contextual Info: Revision 6 RTSX-SU RadTolerant FPGAs UMC FuseLock Designed for Space • • • • • SEU-Hardened Registers Eliminate the Need to Implement Triple-Module Redundancy (TMR) – Immune to Single-Event Upsets (SEU) to LETth > 40 MeV-cm2/mg, – SEU Rate < 10–10 Upset/Bit-Day in Worst-Case