SLY 4 035 34 G Search Results

WMV smd transistor

Abstract: smd mk
Contextual Info: f.con ISO 14001 Alphanumerical product list art. no. page art. no. page art. no. page art. no. page 1706 . G 1831 . ASL . SMD . ASL . SMD . B SM ASLA . ASLG . BADM . BADP . BK 01 32 BL 1 . BL 10 . BL 11 . BL 12 . BL 13 . BL 14 .

955B

Abstract: diode zener ZL 15 932B diode 946b 1SMB5926 1SMB5927 1SMB5928 1SMB5956 926B 932B diode zener
Contextual Info: TAIWAN SEMICONDUCTOR [ s Pb RoHS COMPLIANCE 1SMB5926 - 1SMB5956 3.0 Watts Surface Mount Silicon Zener Diode SMB/DO-214AA .083 2.10 .077(1.95) nI u Features •> -v-y-y- . * .147(3.73) ,137(3.48) * F o r surface m ounted applications in ord er to o ptim ize board sp ace

EP910PC-30

Abstract: EP910PC-40 EP910PC35 EP910PC-35 EP9100c EP910LC-30 EP910J EP910JC30 EP910LC-40 EP910JC-30
Contextual Info: EP910 HIGH-PERFORMANCE 24-MACROCELL ERASABLE PROGRAMMABLE LOGIC DEVICE EPLD D3187. OCTOBER 1988-REVISED AUQUST 1989 DUAL-IN-LINE PAC KA G E • High-Density (Over 900 Gates) Replacement for TTL and 74HC H O P VIEW) clk C 1 V_J40 39 iC 2 • Virtually Zero Standby Power. Typ 20 nA

EP910PC-40

Abstract: EP910LI PACKAGE EP910 texas
Contextual Info: EP910 HIGH-PERFORMANCE 24-MACROCELL ERASABLE PROGRAMMABLE LOGIC DEVICE EPLD D3187, OCTOBER 1988-REVISED AUGUST 19S9 • High-Density (Over 900 Gates) Replacement for TTL and 74HC D U A L-IN -LIN E PAC KAG E (TO P V IE W I C 1 iC 2 ]V c c 39 H i 38 □ i

Contextual Info: 19-1255; Rev 0; 8/97 Low-Power, Dual, 13-Bit Voltage-Output DACs w ith Serial Interface F e a tu re s ♦ 13-Bit Dual DAC with Internal Gain of +2 T h e 3 - w ir e s e r ia l in t e r f a c e is S P I /Q S P I™ a n d M ic ro w ire ™ c o m p a tib le . E a c h D A C h a s a d o u b le buffere d in p u t org a n ize d as an in p u t re g iste r follow ed

Contextual Info: SAB 82538 SAF 82538 SIEM ENS H D LC M ode D etailed R egister D escription In the register description the register addresses are specified by an “offset" relative to the “base addresses' , which are 000, 040, 080. 0C 0, 100, 140, 180, 1C0 for the eight

CXA-L0612-VJL

Abstract: LM12S49 tdk lcd inverter KCA-13 8x 8 led dot matrix BHR-03VS-1 SM02 1g-301 W301th LC98511
Contextual Info: PREPARED BY: SP E C No. L C 9 8 5 1 1 DATE SHARP APPRO VED BY : DATE LIQ U ID C R Y S T A L D IS P L A Y G R O U P S H A R P C O R P O R A ST IO N SPECIFICATION F IL E N o . IS S U PAGE JU N . 15.1998 2 9 P age s R E P R E N T A T T V E D IV IS IO N E N G IN E E R IN G D E P A R T M E N T 1

Behavioral verilog model

Abstract: "li shin" ac adapter
Contextual Info: MACH 5A Family BEYOND PERFORMANCE Fifth G eneration MACH A rchitecture UNIQUE FEATURES ♦ High Densities and l/Os — 6 Macrocell options 128 to 512 — 6 I/O options (74 to 256) — 1 6 - 6 4 o u tp u t enables — Up to 5 I/O options per macrocell — Up to 6 density & I/O options fo r each package

EP910PC-40

Abstract: EP910PC-30 EP910LC-30 bit 3501 Architecture EP910DC-40 EP910LI PACKAGE EP910DC-30 EP910 24-MACROCELL EP910DC
Contextual Info: EP910 HIGH-PERFORMANCE 24-MACROCELL ERASABLE PROGRAMMABLE LOGIC DEVICE EPLD D3187, OCTOBER 1988 —REVISED AUGUST 1&89 DUA L-IN-LINE PACKAGE • High-Density (Over 900 Gates) Replacem ent for TTL and 74H C • Virtually Zero Standby P o w e r. . . Typ 20 |iA

Contextual Info: ADVANCE MT4 L C2M8A1/2 S MEG X 8 WIDE DRAM WIDE DRAM 2 MEG X 8 DRAM 5.0V, S ELF REFRESH (MT4C2M8A1/2 S) 3.0/3.3V, S ELF REFRESH (MT4LC2M8A1/2 S) FEA TU RES PIN ASSIGNMENT (Top View) O PTIO NS M ARKIN G • Timing 60ns access 70ns access 80ns access -6 -7 -8

084BI

Abstract: L084A bl043 I020A at6003-2qi L064A 10104A
Contextual Info: Features High-performance - System Speeds >100 MHz - Flip-flop Toggle Rates > 250 MHz - 1.2 ns/1.5 ns Input Delay - 3.0 ns/6.0 ns Output Delay Up to 204 User l/Os Thousands of Registers Cache Logic Design - Complete/Partial In-System Reconfiguration - No Loss of Data or Machine State

Contextual Info: CY7C43624 CY7C43634/CY7C43644 CY7C43664/CY7C43684 y«^5558S8S88&ik, PRELIMINARY 256/512/1 K/4K/16K x36 x2 Bidirectional Synch ronous FIFO w/ Bus Matching Fully as y n c h ro n o u s and sim u ltan eo u s read and w rite o p eratio n perm itted Features • H ig h -sp eed , low -pow er, B id irectio n al, First-In F irst-O u t

CY7C43642AV

Abstract: CY7C43662AV CY7C43682AV CY7C436X2AV
Contextual Info: - — = C Y rH h b b CY7C43642AV PRELIMINARY CY7C43662AV/CY7C43682AV — 3.3V 1K /4 K /1 6 K x3 6 x2 B idirectiona l S yn ch ro n o u s FIFO Features • F ully a s yn ch ro n o u s and sim u ltan eo u s read and w rite o p e ratio n p erm itted • 3.3 V h ig h -sp eed , low -pow er, b id irec tio n al, First-In FirstO u t F IF O m em o ries

Contextual Info: CY7C341 CY7C341B ^CYPRESS Features • 192 macrocells in 12 LABs • 8 dedicated inputs, 64 bidirectional I/O pins • 0.8-micron double-metal CMOS EPROM technology CY7C341 • Advanced 0.65-micron CMOS technology to increase performance (CY7C341B) • Programmable interconnect array

motorola ar254

Abstract: AR254 book 1977
Contextual Info: AR254 Article Reprint Phase-Locked Loop Design Articles • “Analyze, Don't Estimate, P hase-Locked Loop Performance" • "Optim ize P h a se-L o ck Loops to Meet Your Needs — Or Determine Why You Can t" • “Suppress P h a se-L o ck-Lo o p Sidebands W ithout

Contextual Info: Preliminary Spec. MITSUBISHI LSIs MH32V7245AST -5, -6, -7 _ HYPER PAGE MODE 2415919104 - BIT 33554432 - WORD BY 72 - BIT DYNAMIC RAM DESCRIPTION PIN CONFIGURATION The MH32V7245AST is 33554432-word x 72-bit dynamic ram stacked structural module. This consist of thirty-six

IC 2 5/LKB-0722KA

Contextual Info: CY7C43622 CY7C43632/CY7C43642 CY7C43662/CY7C43682 PRELIMINARY rraaaaarjBF P Y P Pr \ IT QQ «5r \ . I r P , A i 2 5 6 /5 1 2 /1 K /4 K /1 6K x36 x2 Bidirectional S yn ch ro no u s FIFO • F ully a s yn ch ro n o u s and sim u ltan eo u s read and w rite o p e ratio n p erm itted

JN U10

Abstract: CY7C43624 CY7C43634 CY7C43644 CY7C43664 CY7C43684 bq35
Contextual Info: C Y 7C 43624 C Y 7C 43634/C Y 7C 43644 C Y 7C 43664/C Y 7C 43684 P R E L IM IN A R Y w •tiimttrnjÉÉÉÉÉÉÉt m s¿ *c Y éé P.1 . Xn. * . FI . Ì . . S' ï 256/512/1 K/4K/16K x36 x2 Bidirectional Synchronous FIFO w / Bus M atching Features F ully as yn ch ro n o u s and sim u ltan eo u s read an d w rite

SCR SS 3328

Abstract: HD63143 RSC23 IRE18 HD63143A HD63143P
Contextual Info: H 6 D 3 1 4 3 - Universal Pulse Processor UPP-III D escrip tio n • U p to 16 fu n c tio n s a re p ro g ra m m b le from th e MPU in to th e fu n c tio n ta b le (RAM) 24 16-bit u n iv e rsa l re g iste rs (UDR)

8A35

Abstract: ic lm 317 CY7C43623 CY7C43633 CY7C43643 CY7C43663 CY7C43683
Contextual Info: CYPRESS P R E L IM IN A R Y C Y 7C 43623 C Y 7C 43633/C Y 7C 43643 C Y 7C 43663/C Y 7C 43683 256/512/1K/4K/16K x36 Unidirectional Synchronous FIFO w / Bus Matching Features F ully as y n c h ro n o u s and sim u lta n e o u s read and w rite o p e ratio n p erm itted

81c1001

Abstract: aa743 M04I
Contextual Info: October 1989 Edition 3.0 _ — FUJITSU . D A T A S H E E T MB81C1001 - 70/ - 80/ - 10/-12 CMOS 1048576 BIT NIBBLE DYNAMIC RAM CMOS 1,048,576 x 1 BIT NIBBLE MODE DYNAMIC RAM T h e Fujitsu M B 8 1 C 1 0 0 1 is C M O S fu lly decoded dynam ic R A M organized as

tian y1

Abstract: MBA III Thin Quad flat package cypres CY7C43626 CY7C43636 CY7C43646 CY7C43666 CY7C43686 LM 3917 c917
Contextual Info: CY7C43626 CY7C43636/CY7C43646 CY7C43666/CY7C43686 . PRELIMINARY 2 5 6 / 5 1 2 / 1 K / 4 K / 1 6 K x 3 6 / x 1 8 x 2 T ri B u s F I F O Features F ully as yn c h ro n o u s and sim u lta n e o u s read and w rite o p e ratio n p erm itted • H ig h -s p e ed , low -pow er, first-in firs t-o u t F IF O m e m o ­

JDS SB switch

Abstract: CY7C43644V CY7C43664V CY7C43684V CY7C43664V/CY7C43684V
Contextual Info: CY7C43644V CY7C43664V/CY7C43684V PRELIMINARY CYPRESS 3.3V 1K/4K/16K x36 x2 Bidirectional Synchronous FIFO w/ Bus Matching Features — Ic c = 60 m A , lSB= 12 m A F ully a s yn ch ro n o u s and sim u ltan eo u s read and w rite o p e ratio n p erm itted FWFT Mode, Ptease See Errata Attached

Contextual Info: - ^ n n n > CYPHhbo CY7C43622 CY7C43632/CY7C43642 CY7C43662/CY7C43682 PRELIMINARY = 256/512/1K/4K/16K x36 x2 Bidirectional Synchronous FIFO • F ully a s yn ch ro n o u s and sim u ltan eo u s read and w rite o p e ratio n p erm itted Features • H ig h -s p e ed , low -pow er, b id irec tio n al, First-In First-O ut