SLY 4 035 34 G Search Results

EP910PC-30

Abstract: EP910PC-40 EP910PC35 EP910PC-35 EP9100c EP910LC-30 EP910J EP910JC30 EP910LC-40 EP910JC-30
Contextual Info: EP910 HIGH-PERFORMANCE 24-MACROCELL ERASABLE PROGRAMMABLE LOGIC DEVICE EPLD D3187. OCTOBER 1988-REVISED AUQUST 1989 DUAL-IN-LINE PAC KA G E • High-Density (Over 900 Gates) Replacement for TTL and 74HC H O P VIEW) clk C 1 V_J40 39 iC 2 • Virtually Zero Standby Power. Typ 20 nA

EP910PC-40

Abstract: EP910LI PACKAGE EP910 texas
Contextual Info: EP910 HIGH-PERFORMANCE 24-MACROCELL ERASABLE PROGRAMMABLE LOGIC DEVICE EPLD D3187, OCTOBER 1988-REVISED AUGUST 19S9 • High-Density (Over 900 Gates) Replacement for TTL and 74HC D U A L-IN -LIN E PAC KAG E (TO P V IE W I C 1 iC 2 ]V c c 39 H i 38 □ i

Contextual Info: 19-1255; Rev 0; 8/97 Low-Power, Dual, 13-Bit Voltage-Output DACs w ith Serial Interface F e a tu re s ♦ 13-Bit Dual DAC with Internal Gain of +2 T h e 3 - w ir e s e r ia l in t e r f a c e is S P I /Q S P I™ a n d M ic ro w ire ™ c o m p a tib le . E a c h D A C h a s a d o u b le buffere d in p u t org a n ize d as an in p u t re g iste r follow ed

Behavioral verilog model

Abstract: "li shin" ac adapter
Contextual Info: MACH 5A Family BEYOND PERFORMANCE Fifth G eneration MACH A rchitecture UNIQUE FEATURES ♦ High Densities and l/Os — 6 Macrocell options 128 to 512 — 6 I/O options (74 to 256) — 1 6 - 6 4 o u tp u t enables — Up to 5 I/O options per macrocell — Up to 6 density & I/O options fo r each package

Contextual Info: ADVANCE MT4 L C2M8A1/2 S MEG X 8 WIDE DRAM WIDE DRAM 2 MEG X 8 DRAM 5.0V, S ELF REFRESH (MT4C2M8A1/2 S) 3.0/3.3V, S ELF REFRESH (MT4LC2M8A1/2 S) FEA TU RES PIN ASSIGNMENT (Top View) O PTIO NS M ARKIN G • Timing 60ns access 70ns access 80ns access -6 -7 -8

084BI

Abstract: L084A bl043 I020A at6003-2qi L064A 10104A
Contextual Info: Features High-performance - System Speeds >100 MHz - Flip-flop Toggle Rates > 250 MHz - 1.2 ns/1.5 ns Input Delay - 3.0 ns/6.0 ns Output Delay Up to 204 User l/Os Thousands of Registers Cache Logic Design - Complete/Partial In-System Reconfiguration - No Loss of Data or Machine State

Contextual Info: CY7C43624 CY7C43634/CY7C43644 CY7C43664/CY7C43684 y«^5558S8S88&ik, PRELIMINARY 256/512/1 K/4K/16K x36 x2 Bidirectional Synch ronous FIFO w/ Bus Matching Fully as y n c h ro n o u s and sim u ltan eo u s read and w rite o p eratio n perm itted Features • H ig h -sp eed , low -pow er, B id irectio n al, First-In F irst-O u t

CY7C43642AV

Abstract: CY7C43662AV CY7C43682AV CY7C436X2AV
Contextual Info: - — = C Y rH h b b CY7C43642AV PRELIMINARY CY7C43662AV/CY7C43682AV — 3.3V 1K /4 K /1 6 K x3 6 x2 B idirectiona l S yn ch ro n o u s FIFO Features • F ully a s yn ch ro n o u s and sim u ltan eo u s read and w rite o p e ratio n p erm itted • 3.3 V h ig h -sp eed , low -pow er, b id irec tio n al, First-In FirstO u t F IF O m em o ries

Contextual Info: CY7C341 CY7C341B ^CYPRESS Features • 192 macrocells in 12 LABs • 8 dedicated inputs, 64 bidirectional I/O pins • 0.8-micron double-metal CMOS EPROM technology CY7C341 • Advanced 0.65-micron CMOS technology to increase performance (CY7C341B) • Programmable interconnect array

IC 2 5/LKB-0722KA

Contextual Info: CY7C43622 CY7C43632/CY7C43642 CY7C43662/CY7C43682 PRELIMINARY rraaaaarjBF P Y P Pr \ IT QQ «5r \ . I r P , A i 2 5 6 /5 1 2 /1 K /4 K /1 6K x36 x2 Bidirectional S yn ch ro no u s FIFO • F ully a s yn ch ro n o u s and sim u ltan eo u s read and w rite o p e ratio n p erm itted

JN U10

Abstract: CY7C43624 CY7C43634 CY7C43644 CY7C43664 CY7C43684 bq35
Contextual Info: C Y 7C 43624 C Y 7C 43634/C Y 7C 43644 C Y 7C 43664/C Y 7C 43684 P R E L IM IN A R Y w •tiimttrnjÉÉÉÉÉÉÉt m s¿ *c Y éé P.1 . Xn. * . FI . Ì . . S' ï 256/512/1 K/4K/16K x36 x2 Bidirectional Synchronous FIFO w / Bus M atching Features F ully as yn ch ro n o u s and sim u ltan eo u s read an d w rite

8A35

Abstract: ic lm 317 CY7C43623 CY7C43633 CY7C43643 CY7C43663 CY7C43683
Contextual Info: CYPRESS P R E L IM IN A R Y C Y 7C 43623 C Y 7C 43633/C Y 7C 43643 C Y 7C 43663/C Y 7C 43683 256/512/1K/4K/16K x36 Unidirectional Synchronous FIFO w / Bus Matching Features F ully as y n c h ro n o u s and sim u lta n e o u s read and w rite o p e ratio n p erm itted

tian y1

Abstract: MBA III Thin Quad flat package cypres CY7C43626 CY7C43636 CY7C43646 CY7C43666 CY7C43686 LM 3917 c917
Contextual Info: CY7C43626 CY7C43636/CY7C43646 CY7C43666/CY7C43686 . PRELIMINARY 2 5 6 / 5 1 2 / 1 K / 4 K / 1 6 K x 3 6 / x 1 8 x 2 T ri B u s F I F O Features F ully as yn c h ro n o u s and sim u lta n e o u s read and w rite o p e ratio n p erm itted • H ig h -s p e ed , low -pow er, first-in firs t-o u t F IF O m e m o ­

JDS SB switch

Abstract: CY7C43644V CY7C43664V CY7C43684V CY7C43664V/CY7C43684V
Contextual Info: CY7C43644V CY7C43664V/CY7C43684V PRELIMINARY CYPRESS 3.3V 1K/4K/16K x36 x2 Bidirectional Synchronous FIFO w/ Bus Matching Features — Ic c = 60 m A , lSB= 12 m A F ully a s yn ch ro n o u s and sim u ltan eo u s read and w rite o p e ratio n p erm itted FWFT Mode, Ptease See Errata Attached

DP142

Abstract: p139d E2p 49 transistor Transistor z3p tbh 12-38 transistor BJ 102 131 E2p 98 transistor ND1220 pj 75 sx 34
Contextual Info: € E I " C l l b O P S X F a m ily D a ta S h e e t D escription Features • SR A M -based , In -system Program m able • Sw itch M atrix - N on-Blocking - Program m able Bus W idths of 4 ,8 ,1 6 and 32 bits - Id entical and Predictable D elays - O ne-to-O ne, O n e-to-M an y and M any-toO n e C onnections

CY7C43646V

Abstract: CY7C43666V CY7C43686V AEB 015 P
Contextual Info: V CYPRESS CY7C43646V CY7C43666V/CY7C43686V PRELIMINARY 3.3V 1K/4K/16K x36/x18x2 Tri Bus FIFO Features — Ic c = 60 m A , lSB= 12 m A Fully a s yn ch ro n o u s and s im u lta n e o u s read and w rite o p e ratio n p erm itted • For FWFT Mode, Please See Errata Attached

M3766

Abstract: M3865 BE 84 CY7C43646AV CY7C43666AV CY7C43686AV CY7C436X6AV
Contextual Info: V CYPRESS CY7C43646AV PRELIMINARY CY7C43666AV/CY7C43686AV 3.3V 1K/4K/16K x36/x18x2 Tri Bus FIFO Features Fully a s yn ch ro n o u s and s im u lta n e o u s read and w rite o p e ratio n p erm itted • 3.3 V h ig h -sp eed , low -pow er, first-in first-o u t F IF O

Elap 72

Contextual Info: CY7C43642V CY7C43662V/CY7C43682V 3.3V 1K/4K/16K x36 x2 Bidirectional Synchronous FIFO • Fully as yn ch ro n o u s and sim u ltan eo u s read and w rite o p eratio n p erm itted Features • 3.3 V h ig h -sp eed , low -pow er, b id irec tio n al, first-in

Contextual Info: CY7C43646V CY7C43666V/CY7C43686V PRELIMINARY 3.3V 1K/4K/16K x36/x18x2 Tri Bus FIFO Features Fully a s y n c h ro n o u s and sim u lta n e o u s read and w rite o p e ratio n p erm itted • 3.3 V h ig h -sp eed , low -pow er, first-in first-o u t F IF O

R807D

Contextual Info: R8070 *» Rockwell R8070 T1/CEPT PCM Transceiver INTRODUCTION FEATURES The R ockw ell R 8070 T1/C EPT PCM Transceiver is a m onolithic silicon gate C M O S device designed to im ple m en t PCM tra n s­ m itter and receiver functions applied in primary-rate digital carrier

bb 3527

Contextual Info: CY7C43644V CY7C43664V/CY7C43684V PRELIMINARY 3.3V 1K/4K/16K x36 x2 Bidirectional Synchronous FIFO w/ Bus Matching • Fully as yn ch ro n o u s and sim u ltan eo u s read and w rite o p eratio n p erm itted Features • 3.3 V h ig h -sp eed , low -pow er, b id irec tio n al, first-in

Contextual Info: CY7C43643V CY7C43663V/CY7C43683V PRELIMINARY CYPR] 3.3V 1K/4K/16K x36 Unidirectional Synchronous FIFO w / Bus Matching Features F ully a s yn ch ro n o u s and sim u ltan eo u s read and w rite o p e ratio n p erm itted H ig h -s p e ed , low -pow er, U n id ire ctio n al, first-in first-o u t

MB87030

Contextual Info: MB87035/36 SCSI Protocol Controller SPC lor use with Differential or Single-end Drivers E dition 1.0 S e p te m b e r 1989 GENERAL DESCRIPTION The MB87035/36 SCSI Protocol Controller (SPC) is a CMOS LSI circuit specifically designed to control a Small Computer Systems Interface (SCSI). The MB87035/36 is an enhanced version of Fujitsu’s

3686v

Abstract: O17B
Contextual Info: CY7C43646V CY7C43666V/C Y7 C43686V PRELIMINARY 3.3V 1K/4K/16Kx36/x18x2 Tri Bus FIFO • Fully a s y n c h ro n o u s and sim u lta n e o u s read and w rite o p eratio n perm itted Features • 3.3V h ig h -sp eed , low -pow er, first-in firs t-o u t F IF O