SLC64 Search Results

SCAN16512

Abstract: SLC64A
Contextual Info: SCAN16512 Low Voltage Universal 16-bit IEEE 1149.1 Bus Transceiver with TRI-STATE Outputs General Description Features The SCAN16512 is a high speed, low-power universal bus transceiver featuring data inputs organized into two 8-bit bytes with output enable and latch enable control signals.

DS90CF365MTD

Abstract: DS90CF365 DS90C385 DS90C365 DS90C365MTD DS90C385MTD MTD56 SLC64A
Contextual Info: DS90C385/DS90C365 +3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display FPD Link-85 MHz, +3.3V Programmable LVDS Transmitter 18-Bit Flat Panel Display (FPD) Link-85 MHz General Description The DS90C385 transmitter converts 28 bits of LVCMOS/ LVTTL data into four LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link.

Contextual Info: DS90CR287/DS90CR288A +3.3V Rising Edge Data Strobe LVDS 28-Bit Channel Link-85 MHz General Description Features The DS90CR287 transmitter converts 28 bits of LVCMOS/ LVTTL data into four LVDS Low Voltage Differential Signaling data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link.

Contextual Info: SCAN92LV090 www.ti.com SNLS058I – SEPTEMBER 2000 – REVISED APRIL 2013 SCAN92LV090 9 Channel Bus LVDS Transceiver w/ Boundary SCAN Check for Samples: SCAN92LV090 FEATURES DESCRIPTION • • • • The SCAN92LV090A is one in a series of Bus LVDS transceivers designed specifically for the high speed,

Contextual Info: DS90CF386/DS90CF366 +3.3V LVDS Receiver 24-Bit Flat Panel Display FPD Link —85 MHz, +3.3V LVDS Receiver 18-Bit Flat Panel Display (FPD) Link—85 MHz This chipset is an ideal means to solve EMI and cable size problems associated with wide, high speed TTL interfaces.

TTL display 7

Abstract: DS90CF364A DS90CF384A DS90CF384AMTD DS90CF384ASLC MTD56 RGB24
Contextual Info: ご注意：この日本語データシートは参考資料として提供しており内容が最新でない 場合があります。製品のご検討およびご採用に際しては、必ず最新の英文デー タシートをご確認ください。

DS90CF364A

Abstract: DS90CF384A DS90CF384AMTD DS90CF384ASLC MTD56
Contextual Info: DS90CF384A/DS90CF364A +3.3V LVDS Receiver 24-Bit Flat Panel Display FPD Link—65 MHz, +3.3V LVDS Receiver 18-Bit Flat Panel Display (FPD) Link—65 MHz General Description The DS90CF384A receiver converts the four LVDS data streams (Up to 1.8 Gbps throughput or 227 Megabytes/sec

taiyo PSR4000

Abstract: Shipping Trays kostat 10 x 10 nitto hc100 Kostat tray PSR4000 aus5 EPAK EPAK TRAY JEDEC Kostat PSR4000 aus5
Contextual Info: Table of Contents Introduction . 2 CHIP SCALE PACKAGES . 2

Contextual Info: DS90CF366, DS90CF386 www.ti.com SNLS055H – MAY 2004 – REVISED APRIL 2011 DS90CF386/DS90CF366 +3.3V LVDS Receiver 24-Bit Flat Panel Display FPD Link - 85 MHz, +3.3V LVDS Receiver 18-Bit Flat Panel Display (FPD) Link - 85 MHz Check for Samples: DS90CF366, DS90CF386

DS90CF364A

Abstract: DS90CF384A DS90CF384AMTD DS90CF384ASLC MTD56 RGB24
Contextual Info: Converted to nat2000 DTD updated pid source to reflect base segment Modify text on RSKM and spec. 383A as the Tx MH . typo in features corrected (JFG) format corrections (JFG) added FBGA package info (JFG) Added DC spec for PD pin (CW) Added footnotes and modified figures

DS90C383

Abstract: DS90C383MTD DS90CF384 MTD56 RXOUT23
Contextual Info: DS90C383/DS90CF384 +3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display FPD Link— 65 MHz, +3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link— 65 MHz General Description Features The DS90C383 transmitter converts 28 bits of CMOS/TTL data into four LVDS (Low Voltage Differential Signaling) data

SLCE12

Contextual Info: LOW CAPACITANCE SILICON TRANSIENT SUPPRESSOR DIODES DESCRIPTION This specification sheet defines a series of low-capacitance silicon transient suppressors for the protection of AC signal lines. This series employs a standard suppressor in series with a rectifier with the same transient capabilities as the suppressor. The rectifier is also

SLCE16

Abstract: slce51
Contextual Info: LOW CAPACITANCE SILICON TRANSIENT SUPPRESSOR DIODES DESCRIPTION This specification sheet defines a series of low-capacitance silicon transient suppressors for the protection of AC signal lines. This series employs a standard suppressor in series with a rectifier with the same transient capabilities as the suppressor. The rectifier is also

Contextual Info: SCAN92LV090 9 Channel Bus LVDS Transceiver w/ Boundary SCAN General Description The SCAN92LV090A is one in a series of Bus LVDS transceivers designed specifically for the high speed, low power proprietary backplane or cable interfaces. The device operates from a single 3.3V power supply and includes nine

DS90CR287

Abstract: DS90CR287MTD DS90CR287SLC DS90CR288A MTD56 SLC64A LVDS connector 40 pins NAME
Contextual Info: DS90CR287/DS90CR288A +3.3V Rising Edge Data Strobe LVDS 28-Bit Channel Link-85 MHZ General Description Features The DS90CR287 transmitter converts 28 bits of LVCMOS/ LVTTL data into four LVDS Low Voltage Differential Signaling data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link.

fBGA package tray 12 x 19

Abstract: EPAK TRAY FBGA THICK TRAY fbga Substrate design guidelines JEDEC Kostat FBGA EPAK Kostat PSR4000 SLB128B AN-1125
Contextual Info: Table of Contents Introduction . 2 CHIP SCALE PACKAGES . 2

DS90C383

Abstract: DS90C383MTD DS90C383SLC DS90CF384 MTD56
Contextual Info: DS90C383/DS90CF384 +3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display FPD Link—65 MHz, +3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link—65 MHz General Description Features The DS90C383 transmitter converts 28 bits of LVCMOS/ LVTTL data into four LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link.

SLC64A

Abstract: DS90CR287 DS90CR287MTD DS90CR287SLC DS90CR288A MTD56
Contextual Info: DS90CR287/DS90CR288A +3.3V Rising Edge Data Strobe LVDS 28-Bit Channel Link-85 MHz General Description Features The DS90CR287 transmitter converts 28 bits of LVCMOS/ LVTTL data into four LVDS Low Voltage Differential Signaling data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link.

DS90CR285

Abstract: DS90CR285MTD DS90CR285SLC DS90CR286 DS90CR286ASLC MTD56 LVDS out connector 26 pin DS012910 LVDS 40 pin cable
Contextual Info: DS90CR285/DS90CR286 +3.3V Rising Edge Data Strobe LVDS 28-Bit Channel Link-66 MHz General Description Features The DS90CR285 transmitter converts 28 bits of LVCMOS/ LVTTL data into four LVDS Low Voltage Differential Signaling data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link.

DS90C365

Abstract: DS90C385 DS90CF366 DS90CF386 DS90CF386MTD DS90CF386SLC MTD56 SLC64A NATIONAL RX F2
Contextual Info: DS90CF386/DS90CF366 +3.3V LVDS Receiver 24-Bit Flat Panel Display FPD Link—85 MHz, +3.3V LVDS Receiver 18-Bit Flat Panel Display (FPD) Link—85 MHz General Description The DS90CF386 receiver converts the four LVDS data streams (Up to 2.38 Gbps throughput or 297.5 Megabytes/

DS90CF364A

Abstract: DS90CF384A DS90CF384AMTD DS90CF384ASLC MTD56
Contextual Info: DS90CF384A/DS90CF364A +3.3V LVDS Receiver 24-Bit Flat Panel Display FPD Link—65 MHz, +3.3V LVDS Receiver 18-Bit Flat Panel Display (FPD) Link—65 MHz General Description The DS90CF384A receiver converts the four LVDS data streams (Up to 1.8 Gbps throughput or 227 Megabytes/sec

Contextual Info: DS90CR287/DS90CR288A +3.3V Rising Edge Data Strobe LVDS 28-Bit Channel Link-85 MHZ General Description Features The DS90CR287 transmitter converts 28 bits of LVCMOS/ LVTTL data into four LVDS Low Voltage Differential Signaling data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link.

Contextual Info: DS90CR287/DS90CR288A +3.3V Rising Edge Data Strobe LVDS 28-Bit Channel Link-85 MHZ General Description Features The DS90CR287 transmitter converts 28 bits of LVCMOS/ LVTTL data into four LVDS Low Voltage Differential Signaling data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link.

62G3

Contextual Info: SCAN92LV090 9 Channel Bus LVDS Transceiver w/ Boundary SCAN General Description The SCAN92LV090A is one in a series of Bus LVDS transceivers designed specifically for the high speed, low power proprietary backplane or cable interfaces. The device operates from a single 3.3V power supply and includes nine