SKE MHZ Search Results

BUK426-1000A

Abstract: BUK426-1000B BUK426-100
Contextual Info: 7Z39-// Philips Components Data sheet status Product specification date of issue M arch 1991 B U K 426 - 1OO OA/B PowerMOS transistor PHILIPS INTERNATIONAL SkE D • 711082b 004M135 SSI H P H I N GENERAL DESCRIPTION

Contextual Info: I R C H I I - D E M IC O N D U C T O R T 100311 Low Skew 1:9 Differential Clock Driver Features • Low output to output skew ■ 2000V ESD protection ■ 1:9 low ske w clock driver ■ D ifferential inputs and outputs Ordering Code: Logic Symbol Pin Names

Contextual Info: J \MCC PLL CLOCK GENERATOR APPLICATION NOTE INTRODUCTION As to d a y ’s p ersonal co m p u te rs PC and system s push into the 50M hz realm and beyond, the m in im i­ zation of system clock skew becom es m ore im por­ tant. C lock ske w eats into the effective clock period

Contextual Info: MOTOROLA Order this document by MPC961/D SEMICONDUCTOR TECHNICAL DATA Product Preview MPC961P MPC961C Low Voltage Zero Delay Buffer The M P C 9 6 1 is a 2.5V or 3.3V compatible, 1:18 P L L based zero delay buffer. With output frequencies of up to 200M H z, output ske w s of 150ps

Contextual Info: Guaranteed Low Ske w 3.3V C M O S Clock n r i i i o r / l li i f f o r Driver/ßuffer Q u a lity S e m ic o n d u c t o r , I n c . ^3806 advance INFORMATION FEATURES/BENEFITS DESCRIPTION • JEDEC compatible LVTTL level • 10 low skew clock outputs • Monitor output

intel pentium iv

Contextual Info: A D V A N C E IN F O R M A TIO N 12-OUTPUT BiCMOS PLL CLOCK GENERATOR S4LV406 FEATURES GENERAL DESCRIPTION • • • T he S 4LV 406 BiC M O S clock generator provides 12 L V T T L o u tp u ts w ith le ss th a n 3 5 0 p s of ske w . Im plem ented in A M C C 's 1.0p BiC M O S technology,

Contextual Info: CDC304 OCTAL DIVIDE-BY-2 C IR C U IT / C L O C K DRIVER SCAS325A - JULY 1990 - REVISED NOVEMBER 1995 D OR N P A C K A G E Replaces SN74A S304 TOP V IE W M axim um O utp u t Ske w of 1 ns M a x i m u m P u l s e S k e w o f 1. 5 n s Q3 [ 1 T TL -C o m p atible Inputs and Outputs

Contextual Info: IDT74FCT3807/A 3.3V CMOS I - T O - IO CL O C K DRIVER FEATURES: • • • • • • • • • • • • • Available in SOIC, SSOP, QSOP packages 0.5 MICRON CMOS Technology Guaranteed low skew < 350ps max. Very low duty cycle distortion < 350ps (max.)

C635

Abstract: T1EB UCA0 C634 BCX73
Contextual Info: NPISI-Transistoren für NF-Treiber- und Endstufen B CX 73 B CX 74 BCX 73 und BCX 74sind epitaktische NPN-Silizium-Planar-Transistoren im Kunststoffgehäuse 10 A3 DIN 41 868 ähnlich S O T -3 0 . Die Transistoren sind für den Einsatz in NF-Treiber- und Endstufen, sowie für Schalteranwendungen geeignet. Als Komplementär-Transistoren dazu

Asy transistor

Abstract: ASY 15 asy70 Asy 00 ASY48-V germanium transistor asy Q62901-B1 semix igbt GAL ASY50 ASY48
Contextual Info: ASY48 A SY 70 PNP-Transistoren für Schalteranwendungen A S Y 48 und A S Y 70 sind legierte PNP-Germanium-Transistoren im Gehäuse 1 A 3 DIN 41871 TO-1 ähnl. . Die Anschlüsse sind vom Gehäuse elektrisch isoliert. Der Kollektoranschluß wird mit einem roten Punkt am Gehäuserand gekennzeichnet. Die Transistoren sind besonders

Q60204-Y12-B

Abstract: BDV13 Q60204-Y13-D BDY12 BDY13 Q62901-B16-A 510Z5
Contextual Info: NPN-Transistoren für NF-Endstufen und Schalteranwendungen BDY12 BDY13 B D Y 1 2 und B D Y 1 3 sind epitaktische NPN-Silizium-Planar-Leistungstransistoren im Gehäuse 9 A 2 DIN 41 875 S O T -9 . Der Kollektor ist mit dem Gehäuse elektrisch ver­ bunden. Für die isolierte Befestigung der Transistoren auf einem Chassis sind je 1 Glimmer­

VT244A

Abstract: HYB3117805BSJ SOJ-28
Contextual Info: 2M x 72-Bit Dynamic RAM EDO Module ECC - Module HYM 72V2005GS-50/-60 168 pin buffered DIMM Module Preliminary Information • 168 pin JEDEC Standard, Buffered 8 Byte Dual In-Line Memory Module • 1 bank 2 M x 72 organisation • Optimized for ECC applications

SKE 1/17

Abstract: PC10 PD17015 nec 1026
Contextual Info: DATA SHEET MOS INTEGRATED CIRCUIT µPD17015 4-BIT SINGLE-CHIP MICROCONTROLLER FOR PORTABLE RADIOS The µPD17015 is a super low-voltage 4-bit single-chip microcontroller for digital tuning applications. It features a prescaler that can operate at frequencies up to 220 MHz, a PLL synthesizer, and an LCD controller/driver, all

Contextual Info: fax id: 3527 CY2305 CY2309 Low-Cost 3.3V Zero Delay Buffer for PC and SDRAM Features ules and is available in a 16-pin SOIC package. The CY2305 is an 8-pin version of the CY2309. It accepts one reference input, and drives out five low skew clocks. The -1H versions of

Contextual Info: HD74CDCF2509B 140 MHz, 0 to 85 °C Operation 3.3-V Phase-lock Loop Clock Driver HITACHI ADE-205-224C Z Preliminary, 4th. Edition Feb. 1, 1999 Description The HD74CDCF2509B is a high-performance, low-skew, low-jitter, phase-lock loop clock driver. It uses a

Contextual Info: DISTINCTIVE CHARACTERISTICS • 512 X 64-b it versio n of th e po pular M U 9C 1480 C M OS C ontent-add ressable M em o ry C AM T w o M ask reg isters allo w m asking o f individual bits for both w riting and com paring • 64-b it internal data path m ultiplexed ov e r a 16-bit I/O interface

Contextual Info: IDT54/74FCT807BT/CT FAST CMOS 1-TO-10 CLOCK DRIVER Integrated Device Technology, Inc. FEATURES: > 2 0 0 V using machine model C = 20 0p F , R = 0 • Available in DIP, S O IC , S S O P , Q S O P , C erpack and LCC packages V ery low duty cycle distortion < 350ps (max.)

021B2

Abstract: transistor cbj hmv12 pnp germanium transistor 15bis AFY16 BA RV mesa
Contextual Info: Nicht für N eu entw icklun g PNP-Mesatransistor für HF-Anwendungen bis 900 MHz AFY16 A FY 16 ist ein PNP-Germanium-Transistor in Mesa-Techmk um Gehäuse 18 A 4 DIN 41 876 T O -72 . Die Anschlüsse sind vom Gehäuse elektrisch isoliert. Der Transistor A FY 16 ist für

Contextual Info: HD74CDCF2509B 133 MHz, 0 to 85°C Operation 3.3-V Phase-lock Loop Clock Driver HITACHI ADE-205-224A Z Preliminary, 2nd. Edition Nov. 1, 1998 Description The HD74CDCF2509B is a high-performance, low-skew, low-jitter, phase-lock loop clock driver. It uses a

diode SKE 1/17

Abstract: diode SKE 1/16
Contextual Info: 3.3V SYNC DRAM PLL Clock Driver Q QS52510A advance INFORMATION Q u a l it y S em iconductor , I n c . FEATURES/BENEFITS DESCRIPTION • • The Q S 5 2 5 10A is a high perform ance, low skew, low jitter, m ultiple output phase lock loop clock driver. It is designed to interface w ith the high-speed SD R AM

Contextual Info: IDT5T9950/A 2.5V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II JR. INDUSTRIAL TEMPERATURE RANGE 2.5V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II JR. FEATURES: • • • • DESCRIPTION: Ref input is 3.3V tolerant 4 pairs of programmable skew outputs

Contextual Info: DATA SHEET NEC MOS INTEGRATED CIRCUIT 4-BIT SINGLE-CHIP MICROCONTROLLER FOR PORTABLE RADIOS The ¿¡PD17015 is a super low-voltage 4-bit single-chip m icrocontroller for digital tuning applications. It features a prescaler that can operate at frequencies up to 220 MHz, a PLL synthesizer, and an LCD controller/driver, all

Contextual Info: 3.3V SYNC DRAM PLL Clock Driver Q QS52510A advance INFORMATION Q u a l it y S em iconductor , I n c . FEATURES/BENEFITS DESCRIPTION • • The Q S 5 2 5 10A is a high perform ance, low skew, low jitter, m ultiple output phase lock loop clock driver. It is designed to interface w ith the high-speed SD R AM

PS8555

Abstract: PI6C3Q991E PI6C3Q993E QS5V991 QS5V993
Contextual Info: PI6C3Q991E, PI6C3Q993E