SINGLE-CYCLE PROCESSOR Search Results

ST EZ 728

Abstract: ADSP-2181 "analog devices" adsp 2181 and application notes "analog devices" adsp 2181 and byte DMA 2 way splitter, circuit diagram ADSP-2181 ez-kit free software adsp-2181kst, ad1847 DESIGN AND IMPLEMENTATION 16-BIT BARREL SHIFTER SRAM-16K AD1847
Contextual Info: a FEATURES PERFORMANCE 30 ns Instruction Cycle Time @ 5.0 Volts 33 MIPS Sustained Performance 34.7 ns Instruction Cycle Time @ 3.3 Volts Single-Cycle Instruction Execution Single-Cycle Context Switch 3-Bus Architecture Allows Dual Operand Fetches in Every Instruction Cycle

Contextual Info: ANALOG DEVICES FEATURES PERFORMANCE 30 ns Instruction Cycle Time 33 MIPS Sustained Performance Single-Cycle Instruction Execution Single-Cycle Context Switch 3-Bus Architecture Allows Dual Operand Fetches in Every Instruction Cycle Multifunction Instructions

AD1847

Abstract: ADSP-2100 ADSP-2181 ADSP2185L ADSP-2185L
Contextual Info: a FEATURES PERFORMANCE 19 ns Instruction Cycle Time @ 3.3 Volts, 52 MIPS Sustained Performance Single-Cycle Instruction Execution Single-Cycle Context Switch 3-Bus Architecture Allows Dual Operand Fetches in Every Instruction Cycle Multifunction Instructions

strain guage

Abstract: C3189 4 bit barrel shifter circuit for left shift dsp 32 c processor adsp 218x user manual AD1847 ADSP-2100 ADSP-2181 ADSP2185L ADSP-2185L
Contextual Info: a FEATURES PERFORMANCE 19 ns Instruction Cycle Time @ 3.3 Volts, 52 MIPS Sustained Performance Single-Cycle Instruction Execution Single-Cycle Context Switch 3-Bus Architecture Allows Dual Operand Fetches in Every Instruction Cycle Multifunction Instructions

C3174

Abstract: McKenzie transistor c3174 ADSP2187L ADSP-2187L AD1847 ADSP-2100 ADSP-2181 8K24
Contextual Info: a FEATURES PERFORMANCE 19 ns Instruction Cycle Time @ 3.3 Volts, 52 MIPS Sustained Performance Single-Cycle Instruction Execution Single-Cycle Context Switch 3-Bus Architecture Allows Dual Operand Fetches in Every Instruction Cycle Multifunction Instructions

AD1847

Abstract: ADSP2187L ADSP-2187L ADSP-2100 Family EZ-Tools ADSP-2100 ADSP-2181 ADSP-2100 Family Development Tools
Contextual Info: a FEATURES PERFORMANCE 25 ns Instruction Cycle Time @ 3.3 Volts, 40 MIPS Sustained Performance Single-Cycle Instruction Execution Single-Cycle Context Switch 3-Bus Architecture Allows Dual Operand Fetches in Every Instruction Cycle Multifunction Instructions

001C

Abstract: AD1847 ADSP-2100 ADSP-2181 ADSP-2189M
Contextual Info: a FEATURES PERFORMANCE 13.3 ns Instruction Cycle Time @ 2.5 Volts Internal , 75 MIPS Sustained Performance Single-Cycle Instruction Execution Single-Cycle Context Switch 3-Bus Architecture Allows Dual Operand Fetches in Every Instruction Cycle Multifunction Instructions

Contextual Info: ANALOG DEVICES DSP Microcomputer ADSP-2185 FEATURES PERFORMANCE 30 ns Instruction Cycle Time 33 MIPS Sustained Performance Single-Cycle Instruction Execution Single-Cycle Context Switch 3-Bus Architecture Allows Dual Operand Fetches in Every Instruction Cycle

c3605

Abstract: 001C AD1847 ADSP-2100 ADSP-2181 ADSP-2189M ADSP-2100 Family EZ-Tools ADSP-2189MBST-266 CIRCUIT
Contextual Info: a FEATURES PERFORMANCE 13.3 ns Instruction Cycle Time @ 2.5 Volts Internal , 75 MIPS Sustained Performance Single-Cycle Instruction Execution Single-Cycle Context Switch 3-Bus Architecture Allows Dual Operand Fetches in Every Instruction Cycle Multifunction Instructions

CHN 617

Abstract: block diagram for barrel shifter ADSP-2187L
Contextual Info: BACK a FEATURES PERFORMANCE 25 ns Instruction Cycle Time @ 3.3 Volts, 40 MIPS Sustained Performance Single-Cycle Instruction Execution Single-Cycle Context Switch 3-Bus Architecture Allows Dual Operand Fetches in Every Instruction Cycle Multifunction Instructions

Contextual Info: a FEATURES PERFORMANCE 13.3 ns Instruction Cycle Time @ 2.5 Volts Internal , 75 MIPS Sustained Performance Single-Cycle Instruction Execution Single-Cycle Context Switch 3-Bus Architecture Allows Dual Operand Fetches in Every Instruction Cycle Multifunction Instructions

Contextual Info: ANALOG DEVICES DSP Microcomputer ADSP-2186 FEATURES PERFORMANCE 30 ns Instruction Cycle Time 33 MIPS Sustained Performance Single-Cycle Instruction Execution Single-Cycle Context Switch 3-Bus Architecture Allows Dual Operand Fetches in Every Instruction Cycle

evelo

Contextual Info: ANALOG DEVICES DSP Microcomputer AD6F-2186L FEATURES PERFORMANCE 30 ns Instruction Cycle Time 33 M IPS Sustained Performance Single-Cycle Instruction Execution Single-Cycle Context Switch 3-Bus Architecture Allows Dual Operand Fetches in Every Instruction Cycle

24M quartz crystal

Abstract: LXMS 31 009 LXMS 31 011 quartz 24M 1AD4 001C ADSP-2100 ADSP-2181 ADSP-2189M 0x0000-0x1FFF
Contextual Info: ANALOG DEVICES FEATURES PERFORMANCE 13.3 ns Instruction Cycle Tim e @ 2.5 V olts Internal , 75 MIPS Sustained Performance Single-Cycle Instruction Execution Single-Cycle Context Switch 3-Bus Architecture Allow s Dual Operand Fetches in Every Instruction Cycle

Contextual Info: DSP Microcomputer ADSP-2186M a FEATURES Performance 13.3 ns Instruction Cycle Time @ 2.5 V Internal , 75 MIPS Sustained Performance Single-Cycle Instruction Execution Single-Cycle Context Switch 3-Bus Architecture Allows Dual Operand Fetches in Every Instruction Cycle

ADSP-2186M

Abstract: AD73322 ADSP-2100 ADSP-2181 ADSP-2189M load program on ADSP-2189M 2186M
Contextual Info: a DSP Microcomputer ADSP-2186M FEATURES Performance 13.3 ns Instruction Cycle Time @ 2.5 V Internal , 75 MIPS Sustained Performance Single-Cycle Instruction Execution Single-Cycle Context Switch 3-Bus Architecture Allows Dual Operand Fetches in Every Instruction Cycle

adsp 2186 instruction set

Abstract: ka 2186 quartz kds klb x5 LQFP-100 footprint 001C ADSP-2100 ADSP-2181 ADSP-2186 2186B
Contextual Info: ANALOG DEVICES FEATURES PERFORMANCE 25 ns Instruction Cycle Tim e 40 MIPS Sustained Performance Single-Cycle Instruction Execution Single-Cycle Context Switch 3-Bus Architecture A llow s Dual Operand Fetches in Every Instruction Cycle M ultifunction Instructions

Contextual Info: ANALOG DEVICES Preliminary Technical Data FEATURES PERFORMANCE 25 ns Instruction Cycle Tim e 40 MIPS Sustained Performance Single-Cycle Instruction Execution Single-Cycle Context Switch 3-Bus Architecture A llow s Dual Operand Fetches in Every Instruction Cycle

D1592

Contextual Info: BACK a FEATURES PERFORMANCE 19 ns Instruction Cycle Time from 26.32 MHz Crystal @ 3.3 Volts 52 MIPS Sustained Performance Single-Cycle Instruction Execution Single-Cycle Context Switch 3-Bus Architecture Allows Dual Operand Fetches in Every Instruction Cycle

Contextual Info: ANALOG DEVICES FEATURES PERFORMANCE 25 ns Instruction Cycle Tim e 40 MIPS Sustained Performance Single-Cycle Instruction Execution Single-Cycle Context Switch 3-Bus Architecture A llow s Dual Operand Fetches in Every Instruction Cycle M ultifunction Instructions

2184S

Contextual Info: ANALOG DEVICES Preliminary Technical Data FEATURES PERFORMANCE 25 ns Instruction Cycle Tim e 40 MIPS Sustained Performance Single-Cycle Instruction Execution Single-Cycle Context Switch 3-Bus Architecture A llow s Dual Operand Fetches in Every Instruction Cycle

ADSP-2184

Abstract: AD1847 ADSP-2100 ADSP-2181 ADSP2184 emulator el 1600
Contextual Info: a DSP Microcomputer ADSP-2184 Preliminary Technical Data FEATURES PERFORMANCE 25 ns Instruction Cycle Time 40 MIPS Sustained Performance Single-Cycle Instruction Execution Single-Cycle Context Switch 3-Bus Architecture Allows Dual Operand Fetches in Every Instruction Cycle

il6c

Contextual Info: ANALOG DEVICES Preliminary Technical Data FEATURES PERFORMANCE 25 ns Instruction Cycle Tim e 40 MIPS Sustained Performance Single-Cycle Instruction Execution Single-Cycle Context Switch 3-Bus Architecture A llow s Dual Operand Fetches in Every Instruction Cycle

001C

Abstract: AD1847 ADSP-2100 ADSP-2181 ADSP-2184L
Contextual Info: a DSP Microcomputer ADSP-2184L Preliminary Technical Data FEATURES PERFORMANCE 25 ns Instruction Cycle Time 40 MIPS Sustained Performance Single-Cycle Instruction Execution Single-Cycle Context Switch 3-Bus Architecture Allows Dual Operand Fetches in Every Instruction Cycle