SI537XDSPLLSIM Search Results

SI5375

Abstract: Silicon Labs Clock vs. Oscillator Si537xDSPLLsim
Contextual Info: Si5375 4-PLL A NY - F REQUENCY P RECISION C LOCK M ULTIPLIER /J I T T E R A TTENUA TOR Features       Highly integrated, 4–PLL clock  multiplier/jitter attenuator Four independent DSPLLs support any-frequency synthesis and jitter 

Si5324

Abstract: SIWARD 25 MHZ crystal BC1206
Contextual Info: A NY - F R E Q U E N C Y P RECISION C L O C K S Si5316, Si5319, Si5322, S i 5 3 2 3 , S i 5 3 2 4 , S i 5 3 2 5 , Si5326, Si5327, Si5365, Si5366, Si5367, Si5368, Si5369, Si5374, Si5375 F AMILY R EFERENCE M ANUAL Rev. 0.51 12/11 Copyright 2011 by Silicon Laboratories

Contextual Info: Si5374 4-PLL A NY - F REQUENCY P RECISION C LOCK M ULTIPLIER /J I T T E R A TTENUA TOR Features       Highly-integrated, 4 PLL clock  multiplier/jitter attenuator Four independent DSPLLs support any-frequency synthesis and jitter attenuation

metal detector plans schematic

Abstract: Si53xx 530HB121M109DG si5374 Si5324
Contextual Info: Si5374 4-PLL A NY - F REQUENCY P RECISION C LOCK M ULTIPLIER /J I T T E R A TTENUA TOR Features       Highly-integrated, 4 PLL clock multiplier/jitter attenuator Four independent DSPLLs support any-frequency synthesis and jitter attenuation

si5376

Abstract: Si5324
Contextual Info: Si5376 4-PLL A NY - F REQUENCY P RECISION C LOCK M ULTIPLIER /J I T T E R A TTENUA TOR Features          Highly-integrated, 4 PLL clock multiplier/jitter attenuator Four independent DSPLLs support any-frequency synthesis and jitter

Si537xDSPLLsim

Contextual Info: Si5375 4-PLL A NY - F REQUENCY P RECISION C LOCK M ULTIPLIER /J I T T E R A TTENUA TOR Features       Highly integrated, 4–PLL clock  multiplier/jitter attenuator Four independent DSPLLs support any-frequency synthesis  and jitter attenuation

Si8051F340

Abstract: C0603X7R160-104KN
Contextual Info: Si 5 3 7 x - EVB S i537 X -EVB E VALUATION B OARD U SER ’ S G UIDE Description Features The Si5374/75/76 Any Frequency Precision Clocks are based on Silicon Labs 3rd-generation DSPLL technology, which provides any-frequency synthesis in a highly integrated PLL solution that eliminates the need

MEMS Pin diagram with explanation

Abstract: metal detector plans schematic SI5374 Si5324 Si5374B
Contextual Info: Si5374 4-PLL A NY - F REQUENCY P RECISION C LOCK M ULTIPLIER /J I T T E R A TTENUA TOR Features       Highly-integrated, 4 PLL clock  multiplier/jitter attenuator Four independent DSPLLs support any-frequency synthesis and jitter  attenuation

Si53xxRM

Abstract: Si53xx-RM Si5324 19.440 MHz TCXO
Contextual Info: A NY - F R E Q U E N C Y P RECISION C L O C K S Si5316, Si5319, Si5322, S i 5 3 2 3 , S i 5 3 2 4 , S i 5 3 2 5 , Si5326, Si5327, Si5365, Si5366, Si5367, Si5368, Si5369, Si5374, Si5375 F AMILY R EFERENCE M ANUAL Rev. 0.5 6/11 Copyright 2011 by Silicon Laboratories