SI5331 Search Results

Si53314

Abstract: in 5007
Contextual Info: Si53314 1 : 6 L O W J IT TE R U N I V E R S A L B U FF E R / L E V E L T R A N S L A T O R W IT H 2 : 1 I N P U T M U X A N D I N D I V I D U A L O E < 1 . 2 5 G H Z Features        6 differential or 12 LVCMOS outputs  Ultra-low additive jitter: 100 fs rms 

Contextual Info: Si53314 1:6 L O W J I T T E R U NIVE RS AL B UFFER /L EVEL T RANSL ATOR W I T H 2 : 1 I NPUT M UX AND I N D I V I D U A L OE <1.25 GH Z Features    Ordering Information: See page 27. Applications Storage Telecom  Industrial  Servers  Backplane clock distribution

MO-220 7x7 0.4 pitch

Abstract: si5331 Si53313
Contextual Info: Si53313 D UAL 1:5 L OW J I T T E R B UFFER / L EVEL T RANSLATOR <1.25 GH Z Features        10 differential or 20 LVCMOS outputs Ultra-low additive jitter: 100 fs rms  Wide frequency range: 1 MHz to 1.25 GHz  Any-format input with pin selectable

Si53315

Abstract: 44qfn
Contextual Info: Si53315 1 : 1 0 L O W J I TT E R U N I V E R S A L B U F F E R /L E V E L T R A N S L A T O R W IT H 2 : 1 I N P U T M U X A N D I N D I V I D U A L O E < 1 . 2 5 G H Z Features         10 differential or 20 LVCMOS outputs Ultra-low additive jitter: 100 fs rms

rs 422

Abstract: Si53312
Contextual Info: Si53312 1 : 1 0 L OW J I T T E R U NIVERSAL B U FF E R /L EVEL T RANSLATOR WITH 2 : 1 I NPUT M UX <1.25 GH Z Features Ordering Information: See page 25. Applications Q6 Q6 VDDOB 34 37 35 38 39 DIVA 1 33 DIVB SFOUTA[1] SFOUTA[0] 2 32 3 31 SFOUTB[1] SFOUTB[0]

si514

Abstract: SI510
Contextual Info: AN765 T HERMAL A NALYSIS OF S I L I C O N L ABS T I M I N G D EVICES 1. Introduction The junction temperature of semiconductor devices affects reliability and performance of Integrated Circuits ICs , including timing devices. This application note provides the following:

what is slew rate

Contextual Info: AN766 U NDERSTANDING A N D O PTIMIZING C L O C K B UFFER ’ S A D D IT I V E J ITTER P E R F OR MA N C E 1. Introduction This application note details the various contributions to a clock distribution’s buffer’s additive phase noise performance and how to optimize performance without increasing costs.

Si53311

Contextual Info: S i 5 3 3 11 1:6 L O W J I T T E R U NIVERSAL B UFFER /L EVEL T RANSLATOR WITH 2 : 1 I NPUT M UX <1.25 GH Z Features Ordering Information: See page 25. Applications Q2 Q3 Q3 Q4 Q4 27 26 25 DIVA 1 24 DIVB SFOUTA[1] 2 23 SFOUTB[1] SFOUTA[0] 3 22 SFOUTB[0]

Contextual Info: CLOCK AND OSCILLATOR PRODUCT SELECTOR GUIDE SPRING 2013 SP RING 2 013 Clocks and oscillators for communications, computing and consumer applications www.silabs.com/timing Engineering for a mixed-signal world. 2 / C L O C K A N D O S C I L L AT O R S E L E C T O R

J162

Abstract: j142 512 j122 j143 Si5315 MKDSN 1.5 J1213 J1214 C0603X7R160-103KNE N2510-6002RB
Contextual Info: Si 5 3 1 5 - EVB S I 5315-EVB U SER ’ S G UIDE Description The Si5315 Evaluation Board User’s Guide provides for a complete and simple evaluation of the functions, features, and performance of the Si5315-EVB. The Si5315 Synchronous Ethernet/Telecom jitter