SHARP 8MBIT ROM Search Results

PLCC 32 intel package dimensions

Abstract: 845 bios chip intel 845 circuit diagram all chip TSOP 48 thermal resistance TSOP 48 LAYOUT ap623 am 28f040 AP-623 PCB Layout tsop 48 PIN SOCKET
Contextual Info: E AP-623 APPLICATION NOTE Multi-Site Layout Planning with Intel’s Boot Block Flash Memory December 1996 Order Number: 292178-003 Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of

Sharp LJ

Contextual Info: SHARP I SPEC 1*0. 1 MR 9 6 3 0 7 ISSUE: Mar. 29 1996 To i SPECIFICAT IONS Product Type 8M bit MASK ROM LH5G8Pxx LH53FV8P00T-X SRTbis specifications contains 9 pages including the cover. If lou hare any objections, please contact us before issuing purchasing order.

da73

Abstract: D-A73
Contextual Info: CMOS 8M 1M x 8 / 512K x 16 Mask-Programmable ROM With Page Mode FEATURES • 1,048,576 words x 8 bit organization (Byte mode) 524,288 words x 16 bit organization (Word mode) PIN CONNECTIONS 42-PIN DIP TO P VIEW . A ie C • Addressable page: 4 words or 8 bytes

Contextual Info: CMOS 8M 1M X 8/512K x 16 Mask-Programmable ROM LH538500C FEATURES • 1,048,576 words x 8 bit organization PIN CONNECTIONS 42-PIN DIP TO P VIEW (Byte mode) r \ 42 □ n c ^18 C 1• a 17 C 2 41 □ As a7 C 3 40 Zl Ag Ag C 4 39 H A10 a 5 [I 5 38 H An 6 37 H a 12

Contextual Info: I U C “ •i l w O O P D Q O D ■ n n A CMOS 8M 1M x 8 / 512K x 16 w w M a s k - P r o g r a m m a b l e ROM With Page Mode FEATURES • 1,048,576 words x 8 bit organization (Byte mode) 524,288 words x 16 bit organization (Word mode) • Access time: 120 ns (MAX.)

AG393

Abstract: d2625
Contextual Info: LH53V8000 FEATURES • 1,048,576 words x 8 bit organization Byte mode 524,288 words x 16 bit organization (Word mode) CMOS 8M (1M x 8 / 512K x 16) 3 V-Drive Mask-Programmable ROM PIN CONNECTIONS 42-PIN DIP TO P VIEW f [I C 2 41 D A fl C 3 40 □ Ag A.C 4

Contextual Info: L H 5 3 8 P CM O S 8M 1M x 8/512K x 16 Mask-Programmable ROM A FEATURES • 1,048,576 x 8 bit organization (Byte mode) 524,288 x 16 bit organization (Word mode) • Access time: 120 ns (MAX.) PIN CONNECTIONS 42-PIN DIP /* a 18 C T O P VIEW N 1• 42 □ N C

IDA10

Contextual Info: LH538500B FEATURES • • • • PIN CONNECTIONS 1,048,576 x 8 bit organization Byte mode 524,288 x 16 bit organization (Word mode) Access time: 150 ns (MAX.) Power consumption: Operating: 275 mW (MAX.) Standby: 550 CMOS 8M (1M x 8 / 512K x 16) Mask-Programmable ROM

PSEUDO SRAM

Abstract: sharp mask rom
Contextual Info: MEMORIES SF-ASIC 8F-A8IC RAM ★Underdevelopment SF-ASIC RAM is a newly conceptualized memory device developed by Sharp. It allows users to mask any address region within the memory area at the users' wish. The device can also be used A D D R E S S M AP as a conventional Pseudo SRAM, as the device

tsop 48 PIN tray

Contextual Info: LH53FV8500E 8M Mask ROM Model No.: LH5G85XX Spec No.: ELI02111 Issue Date: August 6, 1998 SHARP LH53FV8500E •Handle this document carefully for it contains aaterial protected by international copyright law. Any reproduction, full or in part, of this aaterial is prohibited

Contextual Info: CMOS 8M 1 M x 8/512K x 16 Mask-Program m able ROM LH 538P00B FEATURES • 1,048,576 words x 8 bit organization (Byte mode) 524,288 words x 16 bit organization (Word mode) • Access time: 120 ns (MAX.) PIN CONNECTIONS 42-PIN DIP TOP VIEW / ^18 □ 1• 42 □ NC

Contextual Info: SHARP SPEC No. ISSUE: May 15 1996 T o ; SPECIFICATIONS Product Type_ 8 M F l a s h F i l e M e m o r y L H 2 8 F 8 0 0 S U R — 10 Mo d e l No. L H F 8 0 S 0 8 _ j&This s p e c if ic a tio n s c o n ta in s 44 pages in clu d in g th e cover and appendix.

AA1050

Abstract: marking code maxim label
Contextual Info: SHARP SPEC No. E L 0 9 9 1 9 3 ISSUE: Nov. 26 1997 To ; S P E C I F I CAT I O N S Product Type 8M b it MASK ROM LHMC8 6 xx Model No. L H 5 3 C 8 6 00N &This specifications contains 14 pages including the cover and appendix If you have any objections, please contact us before issuing purchasing order.

LH538

Abstract: LH5380 sharp 8mbit rom 64pin lh538 64pin
Contextual Info: PRELIMINARY LH538000-S FEATURES • Low power supply: 2.6 to 5.5 V C M O S 8M 1M x 8 / 512K x 16 3V-Drive M ask-Program m able ROM PIN CONNECTIONS 4 2 -P IN D IP T O P V IE W f A 42 □ N C ^1 8 C • 1,048,576 x 8 bit organization (Byte mode) 524,288 x 16 bit organization

Contextual Info: CMOS 8M 1M x 8 MROM FEATURES • 1,048,576 x 8 bit organization (Byte mode: BYTE = V,L) 524,288 x 16 bit organization (Word mode: BŸTË = V,H) • Access time: 120 ns (MAX.) Access time in page mode: 50 ns (MAX.) • Supply current: -O p e ra tin g : 85 mA (MAX.)

Contextual Info: CMOS 8M 1 M x 8 MROM FEATURES • 1,048,576 x 8 bit organization (Byte mode: BYTE = V,L) 524,288 x 16 bit organization (Word mode: BŸTË = V,H) PIN CONNECTIONS 56-PIN TSOP TOP VIEW • Access time: 120 ns (MAX.) • Supply current: -O p e ra tin g : 35 mA (MAX.)

Contextual Info: LH53B8P00A FEATURES • 1,048,576 words x 8 bit organization Byte mode CMOS 8M (1M x 8 / 512K x 16) MROM With Page Mode PIN CONNECTIONS 42-PIN DIP TOP VIEW f A l8 E 524,288 words x 16 bit organization (Word mode) 1« A17 IZ 2 •N 42 □ NC 41 D A8 Zi Ag

Contextual Info: LH53B8P00A • 1,048,576 words x 8 bit organization Byte mode PIN CONNECTIONS 42-PIN DIP TOP VIEW s 524,288 words x 16 bit organization (Word mode) A 18 • Access time: 120 ns (MAX.) Page mode: 50 ns (MAX.) □ • Power consumption: Operating: 550 mW (MAX.)

A12E

Contextual Info: PRELIMINARY LH538700A • 1,048,576 words x 8 bit organization • Access time: 100 ns MAX. PIN CONNECTIONS 32-PIN DIP 32-PIN SOP TOP VIEW • Power consumption: Operating: 550 mW (MAX.) Standby: 550 [iW (MAX.) • Static operation • TTL compatible I/O

Contextual Info: LH53BV8600N 8M Mask ROM Model No.: LH5D86xx Spec No.: EL093164 Issue Date: May 8, 1998 SHARP LH53BV8600N •Handle this document carefully for it contains material protected by international copyright law. Any reproduction, full or in part, of this material is prohibited

Contextual Info: LH53B8500 FEATURES • 1,048,576 words x 8 bit organization Byte mode CMOS 8M (1M x 8 / 512K x 16) MROM With Page Mode PIN CONNECTIONS 4 2 -P IN D IP T O P V IE W \ 524,288 words x 16 bit organization (Word mode) A -|8 C • Access time: 150 ns (MAX.) Page mode: 70 ns (MAX.)

12A57

Contextual Info: PRELIMINARY LH538700A FEATURES • 1,048,576 words x 8 bit organization • Access time: 100 ns MAX. CMOS 8M (1M x 8) MROM PIN CONNECTIONS TOP VIEW 32-PIN DIP 32-PIN SOP • Power consumption: Operating: 550 mW (MAX.) I— 1 * • Static operation • TTL compatible I/O

Contextual Info: PRELIMINARY LH538600A FEATURES • 1,048,576 words Byte mode CMOS 8M (1M x 8/512K x 16) High-Speed MROM PIN CONNECTIONS x 8 bit organization 524,288 words x 16 bit organization (Word mode) • BYTE input pin selects bit configuration • Access time: 100 ns (MAX.)

Contextual Info: CMOS 8M 1M x 8 MROM FEATURES • 1,048,576 x 8 bit organization (Byte mode: BYTE = V,L) 524,288 x 16 bit organization (Word mode: BYTE = V,H) PIN CONNECTIONS 44-PIN SOP TOP VIEW s • Access time: 120 ns (MAX.) Access time in page mode: 50 ns (MAX.) C •\9