SERIAL INPUT PARALLEL 18 PIN Search Results

Contextual Info: Product Specification PE4305 50 Ω RF Digital Attenuator 5-bit, 15.5 dB, DC – 4.0 GHz Product Description The PE4305 is a high linearity, 5-bit RF Digital Step Attenuator DSA covering a 15.5 dB attenuation range in 0.5 dB steps, and is pin compatible with the PE430x series. This 50-ohm RF

72V2105

Abstract: 72V265LA IDT72V255LA IDT72V265LA IDT72V295
Contextual Info: 3.3 VOLT CMOS SUPERSYNC FIFO 8,192 x 18 16,384 x 18 PRELIMINARY IDT72V255LA IDT72V265LA Integrated Device Technology, Inc. FEATURES: • Choose among the following memory organizations: IDT72V255LA 8,192 x 18 IDT72V265LA 16,384 x 18 • Pin-compatible with the IDT72V275/72V285 and IDT72V295/

72284

Contextual Info: VARIABLE WIDTH CMOS SUPERSYNC FIFO 32,768 x 18 or 65,536 x 9 65,536 x 18 or 131,072 x 9 FEATURES: • Choose among the following memory organizations: IDT72284 32,768 x 18 or 65,536 x 9 IDT72294 65,536 x 18 or 131,072 x 9 • Pin-compatible with the IDT72261/72271, IDT72255/72265

MAX497

Abstract: MAX4456 MAX4456CPL MAX4456CQH MAX4456EPL MAX4456EQH MAX456
Contextual Info: 19-1389; Rev 0; 10/98 Low-Cost, 8x8 Video Crosspoint Switch Ordering Information PART TEMP. RANGE PIN-PACKAGE MAX4456CPL MAX4456CQH MAX4456EPL MAX4456EQH 0°C to +70°C 0°C to +70°C -40°C to +85°C -40°C to +85°C 40 Plastic DIP 44 PLCC 40 Plastic DIP

2.45 GHz single chip transmitter

Abstract: serdes transceiver 1999 ps-1250 f1
Contextual Info: Gigabit Ethernet SerDes Circuit with Differential PECL Clock Inputs HDMP-1637A SerDes Features • IEEE 802.3z Gigabit Ethernet Compatible, Supports 1250 MBd Gigabit Ethernet • Based on X3T11 “10 Bit Specification” • Low Power Consumption • 10 mm 64-pin PQFP Package

cmos para and or not

Abstract: DL10 sick SM5837AF DL-10
Contextual Info: SM5837AF Variable-length 1H Delay Line LSI NIPPON PRECISION CIRCUITS INC. OVERVIEW PINOUT The SM5837AF is a variable-length delay line LSI. It has 12-bit input/output signal which can be set to undergo a delay in the range of 31 to 2078 delay bits. Maximum operating frequency is 40 MHz, making it

74F674

Abstract: N74F674D N74F674N SRG16
Contextual Info: Philips Semiconductors Product specification 16-bit serial/parallel-in, serial-out shift register 3-State FEATURES 74F674 PIN CONFIGURATION • 16-bit serial I/O shift register • 16-bit parallel-in/serial-out converter • Recirculating serial shifting

TLK2711

Contextual Info: TLK2711 1.6 TO 2.7 GBPS TRANSCEIVER SLLS501 – SEPTEMBER 2001 D 1.6 to 2.7 Gigabits Per Second Gbps D D D D D D D Serializer/Deserializer Hot-Plug Protection High-Performance 80-Pin BGA Microstar Junior Package (GQE) 2.5-V Power Supply for Low Power

Contextual Info: TLK2701 1.6 TO 2.7 GBPS TRANSCEIVER SLLS429C – AUGUST 2000 – REVISED JULY 2003 D D D D D D D 1.6 to 2.7 Gigabits Per Second Gbps Serializer/Deserializer Hot-Plug Protection High-Performance 64-Pin VQFP Thermally Enhanced Package (PowerPAD) 2.5-V Power Supply for Low Power

Contextual Info: TLK2701 1.6 TO 2.7 GBPS TRANSCEIVER SLLS429C – AUGUST 2000 – REVISED JULY 2003 D D D D D D D 1.6 to 2.7 Gigabits Per Second Gbps Serializer/Deserializer Hot-Plug Protection High-Performance 64-Pin VQFP Thermally Enhanced Package (PowerPAD) 2.5-V Power Supply for Low Power

wizardlink

Abstract: SLLA071
Contextual Info: TLK2711 1.6 TO 2.7 GBPS TRANSCEIVER SLLS501 – SEPTEMBER 2001 D 1.6 to 2.7 Gigabits Per Second Gbps D D D D D D D Serializer/Deserializer Hot-Plug Protection High-Performance 80-Pin BGA Microstar Junior Package (GQE) 2.5-V Power Supply for Low Power

MD4332BE

Contextual Info: CMOS M D4330B/M D4332B 30/32 Segment LCD Driver FEB. 1985 Features • • • • C M O S Low power 3 to 18 volt operation On-chip wave-shaping High-speed typ. 3 MHz shift register • Std. 40-pin Dual-ln-Line packages Pin Names Pin Connections MD4330B

Contextual Info: CMOS SUPERSYNC FIFO 8,192x18 16,384x18 FEATURES: • Choose among the following memory organizations: IDT72255LA 8 ,1 9 2 x 1 8 IDT72265LA 16,384x 18 • Pin-compatiblewiththe IDT72V275/72V285and IDT72V295/ 72V2105 SuperSync FIFOs • 10ns read/write cycle time 8ns access time

Contextual Info: TLK2711 1.6 TO 2.7 GBPS TRANSCEIVER SLLS501 – SEPTEMBER 2001 D 1.6 to 2.7 Gigabits Per Second Gbps D D D D D D D Serializer/Deserializer Hot-Plug Protection High-Performance 80-Pin BGA Microstar Junior Package (GQE) 2.5-V Power Supply for Low Power

TLK2711-SP

Contextual Info: TLK2711 1.6 TO 2.7 GBPS TRANSCEIVER SLLS501 – SEPTEMBER 2001 D 1.6 to 2.7 Gigabits Per Second Gbps D D D D D D D Serializer/Deserializer Hot-Plug Protection High-Performance 80-Pin BGA Microstar Junior Package (GQE) 2.5-V Power Supply for Low Power

Contextual Info: TLK2701 1.6 TO 2.7 GBPS TRANSCEIVER SLLS429D − AUGUST 2000 − REVISED MARCH 2008 D 1.6 to 2.7 Gigabits Per Second Gbps D D D D D D Serializer/Deserializer Hot-Plug Protection High-Performance 64-Pin VQFP Thermally Enhanced Package (PowerPAD) 2.5-V Power Supply for Low Power

0x8403

Abstract: 0X00 IEEE1284 OX12PCI840 93C46 national semiconductor
Contextual Info: OX12PCI840 Integrated Parallel Port and PCI interface FEATURE • • • IEEE1284 SPP/EPP/ECP parallel port Single function target PCI controller, fully PCI 2.2 and PCI Power Management 1.0 compliant 2 multi-purpose IO pins which can be configured as interrupt input pins

Contextual Info: ispLSI 6192 Lattica High Density Programmable Logic with Dedicated Memory and Register/Counter Modules \Semiconductor i Corporation — 96 I/O Pins with Input Registers — Security Cell Prevents Unauthorized Design C opy­ ing Features A FAMILY OF HIGHLY INTEGRATED, CELL-BASED,

72V2101

Abstract: 72V2111 IDT72V2101 IDT72V2101L IDT72V2111 72V2111L10
Contextual Info: 3.3 VOLT HIGH DENSITY CMOS SUPERSYNC FIFO 262,144 x 9 524,288 x 9 PRELIMINARY IDT72V2101 IDT72V2111 Integrated Device Technology, Inc. FEATURES: • Choose among the following memory organizations: IDT72V2101 262,144 x 9 IDT72V2111 524,288 x 9 • Pin-compatible with the IDT72V261/72V271 and the

74F673A

Abstract: 74F673APC 74F673ASC 74F673ASPC M24B MS-013 N24A N24C
Contextual Info: Revised August 1999 74F673A 16-Bit Serial-In, Serial/Parallel-Out Shift Register General Description Features The 74F673A contains a 16-bit serial-in, serial-out shift register and a 16-bit Parallel-Out storage register. A single pin serves either as an input for serial entry or as a 3STATE serial output. In the Serial-Out mode, the data recirculates in the shift register. By means of a separate clock,

Contextual Info: TLK3104SCGNT 3.125ĆGbps QUAD SERIAL BACKPLANE TRANSCEIVER SLLS537 – SEPTEMBER 2002 D 3.125 Gbps Per Port Providing 10-Gbps D D D D D D D Data Throughput Support Transmit Only, Receiver Only, Transceiver and Repeater Functions in a Single Chip Through Configuration Pins

72V281

Abstract: 72V291 IDT72V281 IDT72V291
Contextual Info: 3.3 VOLT CMOS SUPERSYNC FIFO 65,536 x 9 131,072 x 9 PRELIMINARY IDT72V281 IDT72V291 Integrated Device Technology, Inc. FEATURES: • Choose among the following memory organizations: IDT72V281 65,536 x 9 IDT72V291 131,072 x 9 • Pin-compatible with the IDT72V261/72V271 SuperSync

Contextual Info: Cl Preliminary Am7968/Am7969-175 Advanced Micro Devices TAXIchip Integrated Circuits DISTINCTIVE CHARACTERISTICS • Parallel TTL bus interface - Eight Data and four Command Pins - or nine Data and three Command Pins - or ten Data and two Command Pins ■

Contextual Info: TLK3101 2.5 Gbps to 3.125 Gbps TRANSCEIVER SCAS649A – AUGUST 2000 – REVISED FEBRUARY 2001 D D D D D D Hot-Plug Protection 2.5 Gigabits to 3.125 Gigabits Per Second Gbps Serializer/Deserializer High Performance 64-Pin VQFP Thermally Enhanced Package (PowerPAD)