SERIAL INPUT PARALLEL 18 PIN Search Results

HEF4021

Contextual Info: HEF4021B 8-bit static shift register Rev. 8 — 18 November 2011 Product data sheet 1. General description The HEF4021B is an 8-bit static shift register parallel-to-serial converter with a synchronous serial data input (DS), a clock input (CP), an asynchronous active HIGH

Contextual Info: 19-3943; Rev 1; 8/06 27-Bit, 2.5MHz to 42MHz DC-Balanced LVDS Deserializers The MAX9248/MAX9250 digital video serial-to-parallel converters deserialize a total of 27 bits during data and control phases. In the data phase, the LVDS serial input is converted to 18 bits of parallel video data and in the control phase, the input is converted to 9 bits of parallel control data. The separate video and control phases take

Contextual Info: 19-3943; Rev 1; 8/06 27-Bit, 2.5MHz to 42MHz DC-Balanced LVDS Deserializers The MAX9248/MAX9250 digital video serial-to-parallel converters deserialize a total of 27 bits during data and control phases. In the data phase, the LVDS serial input is converted to 18 bits of parallel video data and in the control phase, the input is converted to 9 bits of parallel control data. The separate video and control phases take

Contextual Info: 19-3943; Rev 1; 8/06 27-Bit, 2.5MHz to 42MHz DC-Balanced LVDS Deserializers The MAX9248/MAX9250 digital video serial-to-parallel converters deserialize a total of 27 bits during data and control phases. In the data phase, the LVDS serial input is converted to 18 bits of parallel video data and in the control phase, the input is converted to 9 bits of parallel control data. The separate video and control phases take

MAX9217

Abstract: MAX9247 MAX9248 MAX9250 MAX9250ECM MAX9250ETM 3248L
Contextual Info: 19-3943; Rev 0; 1/06 27-Bit, 2.5MHz-to-42MHz DC-Balanced LVDS Deserializers The MAX9248/MAX9250 digital video serial-to-parallel converters deserialize a total of 27 bits during data and control phases. In the data phase, the LVDS serial input is converted to 18 bits of parallel video data and in the control phase, the input is converted to 9 bits of parallel control data. The separate video and control phases take

c485

Contextual Info: 19-3557; Rev 0; 2/05 27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Deserializer The MAX9218 digital video serial-to-parallel converter deserializes a total of 27 bits during data and control phases. In the data phase, the LVDS serial input is converted to 18 bits of parallel video data and in the control

MAX9217

Abstract: MAX9218 MAX9218ECM MAX9218ETM
Contextual Info: 19-3557; Rev 2; 10/05 27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Deserializer The MAX9218 digital video serial-to-parallel converter deserializes a total of 27 bits during data and control phases. In the data phase, the LVDS serial input is converted to 18 bits of parallel video data and in the control

Contextual Info: 19-3557; Rev 3; 2/08 27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Deserializer The MAX9218 digital video serial-to-parallel converter deserializes a total of 27 bits during data and control phases. In the data phase, the LVDS serial input is converted to 18 bits of parallel video data and in the control

25 pin parallel connector

Abstract: ic 9945 a 8 pin notes on serial communication MAX232 Parallel-Printer Interface IC EDE1400 MAX232 connection TTL RS232 Level Converter ic max232 rs 232 level converter ic max232 serial port to ttl using max232
Contextual Info: EDE1400 Serial to Parallel-Printer Interface IC EDE1400 1 STROBE BUSY 18 Printer BUSY Line Serial Data Input 2 Serial In Flow 17 Hardware Handshaking PC Only Printer STROBE Line Connect to +5V DC 3 +5V OSC1 16 Oscillator Connection Connect to +5V DC 4 +5V

MAX9217

Abstract: MAX9218 MAX9218ECM MAX9218ETM rgbout video in RGBout
Contextual Info: 19-3557; Rev 5; 8/09 KIT ATION EVALU E L B A AVAIL 27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Deserializer The MAX9218 digital video serial-to-parallel converter deserializes a total of 27 bits during data and control phases. In the data phase, the LVDS serial input is converted to 18 bits of parallel video data and in the control

Contextual Info: 19-3557; Rev 5; 8/09 KIT ATION EVALU E L B A AVAIL 27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Deserializer The MAX9218 digital video serial-to-parallel converter deserializes a total of 27 bits during data and control phases. In the data phase, the LVDS serial input is converted to 18 bits of parallel video data and in the control

Contextual Info: SBX1601A IL00 8- OR 10-BIT PARALLEL-TO-SERIAL CONVERTER —BOTTOM VIEW— INDEX 29 1 2 3 36 37 4 5 6 7 8 9 TTL/ECL 10 6 11 35 12 34 13 33 7 8 9 10 11 14 12 32 15 31 13 14 16 30 29 15 17 16 18 17 18 28 27 26 25 24 23 22 21 20 19 19 20 INPUT D9X - D0X, D9Y - D0Y

Hex schmitt trigger ecl

Abstract: ttl to ecl converter GS9000DCPJE3 GS9000DCTJE3 GS9000D GS9000DCPJ GS9000DCTJ GS9025A GS9035A GS7025
Contextual Info: GENLINX II GS9000D Serial Digital Decoder DATA SHEET DEVICE DESCRIPTION • fully compatible with SMPTE 259M-ABC The GS9000D is a CMOS integrated circuit specifically designed to deserialize SMPTE 259M serial digital signals at data rates up to 270Mb/s. The GS9000D is a pin and

SRG8 Multiplexer

Abstract: 74F322 N74F322D N74F322N 132-6d 93020
Contextual Info: Philips Semiconductors Product specification 8-bit serial/parallel register with sign extend 3-State FEATURES 74F322 PIN CONFIGURATION • Multiplexed parallel I/O ports • Separate serial input and output • Sign extend function • 3-State outputs for bus applications

72V2105

Abstract: 72V265LA IDT72V255LA IDT72V265LA IDT72V295
Contextual Info: 3.3 VOLT CMOS SUPERSYNC FIFO 8,192 x 18 16,384 x 18 PRELIMINARY IDT72V255LA IDT72V265LA Integrated Device Technology, Inc. FEATURES: • Choose among the following memory organizations: IDT72V255LA 8,192 x 18 IDT72V265LA 16,384 x 18 • Pin-compatible with the IDT72V275/72V285 and IDT72V295/

72V2105

Abstract: IDT72255LA IDT72265LA IDT72V295
Contextual Info: CMOS SUPERSYNC FIFO 8,192 x 18 16,384 x 18 PRELIMINARY IDT72255LA IDT72265LA Integrated Device Technology, Inc. FEATURES: • Choose among the following memory organizations: IDT72255LA 8,192 x 18 IDT72265LA 16,384 x 18 • Pin-compatible with the IDT72V275/72V285 and IDT72V295/

72V275

Abstract: IDT72V275 IDT72V285 72V285
Contextual Info: 3.3 VOLT CMOS SUPERSYNC FIFO 32,768 x 18 65,536 x 18 PRELIMINARY IDT72V275 IDT72V285 Integrated Device Technology, Inc. FEATURES: • Choose among the following memory organizations: IDT72V275 32,768 x 18 IDT72V285 65,536 x 18 • Pin-compatible with the IDT72V255/72V265 SuperSync

IDT72275

Abstract: IDT72285
Contextual Info: CMOS SUPERSYNC FIFO 32,768 x 18 65,536 x 18 PRELIMINARY IDT72275 IDT72285 Integrated Device Technology, Inc. FEATURES: • Choose among the following memory organizations: IDT72275 32,768 x 18 IDT72285 65,536 x 18 • Pin-compatible with the IDT72255LA/72265LA SuperSync

Contextual Info: CMOS SUPERSYNC FIFO 32,768 x 18 65,536 x 18 PRELIMINARY IDT72275 IDT72285 Integrated Device Technology, Inc. FEATURES: • Choose among the following memory organizations: IDT72275 32,768 x 18 IDT72285 65,536 x 18 • Pin-compatible with the IDT72255LA/72265LA SuperSync

72V2105

Abstract: 72V2105L10 72V295 IDT72V2105 IDT72V295 72V295L15
Contextual Info: 3.3 VOLT HIGH DENSITY CMOS SUPERSYNC FIFO 131,072 x 18 262,144 x 18 PRELIMINARY IDT72V295 IDT72V2105 Integrated Device Technology, Inc. FEATURES: • Choose among the following memory organizations: IDT72V295 131,072 x 18 IDT72V2105 262,144 x 18 • Pin-compatible with the IDT72V255/72V265 and the

Contextual Info: Product Specification PE4305 50 Ω RF Digital Attenuator 5-bit, 15.5 dB, DC – 4.0 GHz Product Description The PE4305 is a high linearity, 5-bit RF Digital Step Attenuator DSA covering a 15.5 dB attenuation range in 0.5 dB steps, and is pin compatible with the PE430x series. This 50-ohm RF

RESET1-70

Contextual Info: CMOS SuperSync FIFO 32,768 x 18 65,536 x 18 • FEATURES: • • • • • • • • • • • • • • Choose among the following memory organizations: IDT72275 — 32,768 x 18 IDT72285 — 65,536 x 18 Pin-compatible with the IDT72255LA/72265LA SuperSync FIFOs

72V2105

Abstract: IDT72V255LA IDT72V265LA IDT72V295 Transfer Clock in FWFT
Contextual Info: 3.3 VOLT CMOS SuperSync FIFO 8,192 x 18 16,384 x 18 FEATURES: • • • • • • • • • • • • • • • • • Choose among the following memory organizations: IDT72V255LA 8,192 x 18 IDT72V265LA 16,384 x 18 Pin-compatible with the IDT72V275/72V285 and IDT72V295/

72V2105

Abstract: 72V265LA IDT72V255LA IDT72V265LA IDT72V295
Contextual Info: 3.3 VOLT CMOS SUPERSYNC FIFO 8,192 x 18 16,384 x 18 PRELIMINARY IDT72V255LA IDT72V265LA Integrated Device Technology, Inc. FEATURES: • Choose among the following memory organizations: IDT72V255LA 8,192 x 18 IDT72V265LA 16,384 x 18 • Pin-compatible with the IDT72V275/72V285 and IDT72V295/