SD3B Search Results

RECTIFER

Abstract: S463CA S463FB S463GC S463GE S463IH
Contextual Info: R S H ELECTRON/SENSITRÔN IflE D • ?SD3bS0 OOOQÔÛ' i & ■ ~PZ3> - 0~7 SENS/TRON SEMICONDUCTOR 221 Wesf Industry C ourt • Deer Park, N Y 11729 Telephone: 516 586-7600 FAX 516 242 9798 TECHNICAL SPECIFICATIONS AVAILABLE WITH JAN, JANTX OR JANTXV DIODES

BC136

Abstract: ADSP-21160 ADSP-21161 ADSP-21362 ADSP-21363 ADSP-21364 ADSP-21365 ADSP-21366 key board mtm 8 pins key board mtm
Contextual Info: SHARC Processors SUMMARY DEDICATED AUDIO COMPONENTS High performance 32-bit/40-bit floating point processor optimized for high performance audio processing Single-instruction, multiple-data SIMD computational

Contextual Info: \ _ _ _ _ _ _ _ 1£ S D - 3 9 9 Q 0 - 0 10 1 BEAU 90 fH 900V 10A \\ NOTES; MATERIAL: SEE TABLE FINISHES; SEE TABLE PRODUCT SPECIFICATION; NOT PACKAGING; NET REQUIRED NATES WITH; 90 SERIES PLOGGABLE TERMINAL BLOCK INCH DIMS ARE SHOWN IN PARENTHESIS XXX "XX" REFERS TO THE NOMBER OF CIRCUIT POSITIONS

ADSP-21160

Abstract: ADSP-21161 ADSP-21364 CP-1201 ADSP-21364SBSQZENG tbdm
Contextual Info: a SHARC Processor ADSP-21364 Preliminary Technical Data SUMMARY On-chip memory—3M bit of on-chip SRAM and a dedicated 4M bit of on-chip mask-programmable ROM Code compatible with all other members of the SHARC family The ADSP-21364 is available with a 333 MHz core instruction

ADSP-21362KBC

Abstract: L05 SMD 4604 inverter A08 smd transistor bottle counter IEEE format transistor SMD n03 ADSP-21160 ADSP-21161 ADSP-21362 CP-1201
Contextual Info: a SHARC Processor ADSP-21362 SUMMARY High performance 32-bit/40-bit floating-point processor optimized for high performance automotive audio processing Single-instruction, multiple-data SIMD computational architecture On-chip memory—3M bit of on-chip SRAM

sd4b

Abstract: key board mtm 8 pins
Contextual Info: SHARC Processors SUMMARY DEDICATED AUDIO COMPONENTS High performance 32-bit/40-bit floating point processor optimized for high performance audio processing Single-instruction, multiple-data SIMD computational

ADSP-21266

Abstract: ADSP-21160 ADSP-21161 ADSP21266
Contextual Info: SHARC Embedded Processor ADSP-21266 SUMMARY High performance 32-bit/40-bit floating-point processor optimized for high performance audio processing Code compatibility—at assembly level, uses the same instruction set as other SHARC DSPs The ADSP-21266 processes high performance audio while

ADSP-21160

Abstract: ADSP-21161 ADSP21261 ADSP-21261
Contextual Info: SHARC Embedded Processor ADSP-21261 a SUMMARY KEY FEATURES High performance 32-bit/40-bit floating-point processor Code compatibility—at assembly level, uses the same instruction set as other SHARC DSPs Single-instruction multiple-data SIMD computational architecture—two 32-bit IEEE floating-point/32-bit fixed-point/

Contextual Info: a SHARC Processor ADSP-21362 Preliminary Technical Data SUMMARY High performance 32-bit/40-bit floating-point processor optimized for high performance automotive audio processing Single-Instruction Multiple-Data SIMD computational architecture On-chip memory—3M bit of on-chip SRAM

Contextual Info: a SHARC Processor ADSP-21365/ADSP-21366 Preliminary Technical Data SUMMARY Single-Instruction Multiple-Data SIMD computational architecture On-chip memory—3M bit of on-chip SRAM and a dedicated 4M bit of on-chip mask-programmable ROM Code compatible with all other members of the SHARC family

AD150

Contextual Info: a SHARC Processor ADSP-21364 Preliminary Technical Data SUMMARY On-chip memory—3M bit of on-chip SRAM and a dedicated 4M bit of on-chip mask-programmable ROM Code compatible with all other members of the SHARC family The ADSP-21364 is available with a 333 MHz core instruction

TP2G

Abstract: BPV32 5w100 TOSHIBA MARK C56 CSB503F30 PB001 PB111 TA1310N LF 256H T26G
Contextual Info: TOSHIBA TENTATIVE TA1310N TOSHIBA BIPOLAR LINEAR INTEGRATED CIRCUIT SILICON MONOLITHIC T A 1 3 1 ON NTSC VIDEO, CHROMA, DEFRECTION, AND DEC. DISTORTION COMPENSATION IC FOR YUV INTERFACE TA1310N is Video Chroma and defrection signal. Processing IC for NTSC. On a 56-pin shrink DIP package.

sharc ADSP-21xxx general block diagram

Abstract: block diagram of ADSP21xxx SHARC processor sharc 21xxx architecture block diagram 4x4 barrel shifter sharc ADSP-21xxx architecture diagram sharc ADSP21xxx architecture ADSP-21160 ADSP-21161 ADSP-21266 JC JB jt
Contextual Info: PRELIMINARY TECHNICAL DATA S a High Performance SHARC Audio Processor ADSP-21266 Preliminary Technical Data SUMMARY High performance 32-bit/40-bit floating point processor optimized for audio processing The ADSP-21266 processes high performance audio while enabling low system costs

block diagram of ADSP21xxx SHARC processor

Abstract: sharc ADSP-21xxx general block diagram sharc ADSP-21xxx architecture diagram ADSP-21160 ADSP-21161 ADSP-21262 sharc ADSP-21xxx architecture INSTRUCTION SET JC JB jt
Contextual Info: PRELIMINARY TECHNICAL DATA S a High Performance Floating-Point Processor ADSP-21262 Preliminary Technical Data SUMMARY High performance 32-bit floating-point processor optimized for high precision signal processing applications Single-Instruction Multiple-Data SIMD computational

key board mtm 8 pins

Abstract: BC136 144-Lead LQFP_EP sharc iir filter ADSP-21160 ADSP-21161 ADSP-21362 ADSP-21363 max33 ADSP-21365
Contextual Info: SHARC Processors SUMMARY DEDICATED AUDIO COMPONENTS High performance 32-bit/40-bit floating point processor optimized for high performance audio processing Single-instruction, multiple-data SIMD computational

sis661fx

Abstract: GS1117Y ICS952013 d7677 LM393R hitachi ha md50 sis 963l SRP11 M661MX sis 741gx
Contextual Info: 5 4 3 321 V.1.0 2 Clock Gen. Pentium-M / Celeron-M CPU Sideband Bus RTC,VCC3,VCC5 PAGE 9 1 DC_IN Select PAGE 26 PAGE 30 Thermal D D PAGE 2,3,4 Clock Buffer PAGE 10 ECVCC/+5VAUX 400M/533M PAGE 31 CRT Memory Bus North Bridge PAGE 13 SiS M661GX / FX LVDS Board

dts master audio DL 1200

Abstract: 3x3 bit parallel multiplier 4604 CMOS Dolby prologic ADSP21365 ADSP-21365 CP-1201
Contextual Info: a SHARC Processor ADSP-21365/ADSP-21366 Preliminary Technical Data SUMMARY Single-Instruction Multiple-Data SIMD computational architecture On-chip memory—3M bit of on-chip SRAM and a dedicated 4M bit of on-chip mask-programmable ROM Code compatible with all other members of the SHARC family

Contextual Info: SHARC Processor ADSP-21267 Preliminary Technical Data SUMMARY DAI incorporates two Precision Clock Generators PCG , and an Input Data Port (IDP) that includes a Parallel Data Acquisition Port (PDAP), and three programmable timers, all under software control by the Signal Routing Unit (SRU)

Contextual Info: LM27313 www.ti.com SNVS487D – DECEMBER 2006 – REVISED APRIL 2013 LM27313/LM27313-Q1 Check for Samples: LM27313 FEATURES DESCRIPTION • The LM27313 switching regulator is a current-mode boost converter with a fixed operating frequency of 1.6 MHz. 1 2 •

ADSP21267

Abstract: ADSP-21267
Contextual Info: SHARC Processor ADSP-21267 Preliminary Technical Data SUMMARY DAI incorporates two precision clock generators PCG , and an input data port (IDP) that includes a parallel data acquisition port (PDAP), and three programmable timers, all under software control by the signal routing unit (SRU)

Contextual Info: CMOS SyncBiFlFO 256x36x2, 512x36x2, 1024x36x2 IDT723622 IDT723632 IDT723642 Integrated D evice Technology, Inc. FEATURES: • Free-running CLKA and CLKB may be asynchronous or coincident simultaneous reading and writing of data on a single clock edge is permitted

AD150

Abstract: ADSP-21160 ADSP-21161 ADSP-21364 CP-1201 sharc iir filter ADSP 21364 sport control register
Contextual Info: a SHARC Processor ADSP-21364 Preliminary Technical Data SUMMARY On-chip memory—3M bit of on-chip SRAM and a dedicated 4M bit of on-chip mask-programmable ROM Code compatible with all other members of the SHARC family The ADSP-21364 is available with a 333 MHz core instruction

L05 SMD

Abstract: CRYSTAL smd trw ADSP-21161 reference manual bc136 A07 smd A08 smd transistor analog devices m01 n10 smd 6-pin spi flash parallel port transistor SMD n03
Contextual Info: SHARC Embedded Processor ADSP-21266 SUMMARY High performance 32-bit/40-bit floating-point processor optimized for high performance audio processing Code compatibility—at assembly level, uses the same instruction set as other SHARC DSPs Processes high performance audio while enabling low

Contextual Info: g B 7 6 5 4 2 3 SD-39BB0-002 "XX" CIRCUITS EQUALLY SPACED e 5,08 [TOO] m. Z-Z 10,5 5,2 [,20] [ .41 ] 5,4 [ ,21 ] NOTES 1, 2, 3, 4, 5, G, 7, MATERIAL: SEE TABLE FINISHES: SEE TABLE ERDOUET SPEEIFIEATIDN NET REBBIRED PACKAGING: NOT REBBIRED MATES WITH: NONE