SD2B Search Results

b07 p03

Abstract: HSP50216 thermal SD2A
Contextual Info: A_15 A_14 A_13 A_12 A_11 A_10 A_09 A_08 A_07 A_06 A_05 A_04 A_03 A_02 A_01 A_00 ENIAb Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc U? HSP50216 SD1A SD2A SYNCA SD1B SD2B SYNCB SD1C SD2C SYNCC B_15 B_14 B_13 B_12 B_11 B_10 B_09 B_08 B_07 B_06 B_05 B_04 B_03

BC136

Abstract: ADSP-21160 ADSP-21161 ADSP-21362 ADSP-21363 ADSP-21364 ADSP-21365 ADSP-21366 key board mtm 8 pins key board mtm
Contextual Info: SHARC Processors SUMMARY DEDICATED AUDIO COMPONENTS High performance 32-bit/40-bit floating point processor optimized for high performance audio processing Single-instruction, multiple-data SIMD computational

LG 631 IC

Abstract: SDXC pin diagram of tle 7203 F804 F808 HSP50216 HSP50216KI tle 8209 e SD2C tle 8209
Contextual Info: HSP50216 TM Data Sheet tle P5 6 jec rnn ra abl ital n ver tho w rsi por n, ico cto Four-Channel Programmable Digital DownConverter The HSP50216 Quad Programmable Digital DownConverter QPDC) is designed for high dynamic range applications such as cellular basestations where multiple channel processing is

TA1291N

Abstract: Ta 1291n GBF flyback TA1291
Contextual Info: TO SHIBA TENTATIVE T A 12 91 N TOSHIBA BIPOLAR LINEAR INTEGRATED CIRCUIT SILICON MONOLITHIC TA 1 2 9 1 N NTSC VIDEO, CHROMA, DEFRECTION, AND DEC. DISTORTION COMPENSATION IC FOR YUV INTERFACE AND ACB WITH TA1291N is Video Chroma and defrection signal. Processing IC for NTSC. On a 56 pin shrink DIP package.

SDXC

Abstract: UMTS receiver SD2B HSP50216 ISL5216 ISL5217 SD1D cic compensation filter
Contextual Info: Use of HSP50216 and ISL5216 QPDC in Wideband Applications - UMTS TM Application Note April 2001 AN9927 Authors: Aaron Algiere, Dejan Radic Description This document will explain how to use Intersil’s Quad Programmable Down Converters, the HSP50216 and ISL5216, for the Wideband Applications, in particular UMTS.

ADSP-21160

Abstract: ADSP-21161 ADSP-21364 CP-1201 ADSP-21364SBSQZENG tbdm
Contextual Info: a SHARC Processor ADSP-21364 Preliminary Technical Data SUMMARY On-chip memory—3M bit of on-chip SRAM and a dedicated 4M bit of on-chip mask-programmable ROM Code compatible with all other members of the SHARC family The ADSP-21364 is available with a 333 MHz core instruction

ADSP-21362KBC

Abstract: L05 SMD 4604 inverter A08 smd transistor bottle counter IEEE format transistor SMD n03 ADSP-21160 ADSP-21161 ADSP-21362 CP-1201
Contextual Info: a SHARC Processor ADSP-21362 SUMMARY High performance 32-bit/40-bit floating-point processor optimized for high performance automotive audio processing Single-instruction, multiple-data SIMD computational architecture On-chip memory—3M bit of on-chip SRAM

sd4b

Abstract: key board mtm 8 pins
Contextual Info: SHARC Processors SUMMARY DEDICATED AUDIO COMPONENTS High performance 32-bit/40-bit floating point processor optimized for high performance audio processing Single-instruction, multiple-data SIMD computational

ADSP-21266

Abstract: ADSP-21160 ADSP-21161 ADSP21266
Contextual Info: SHARC Embedded Processor ADSP-21266 SUMMARY High performance 32-bit/40-bit floating-point processor optimized for high performance audio processing Code compatibility—at assembly level, uses the same instruction set as other SHARC DSPs The ADSP-21266 processes high performance audio while

ADSP-21160

Abstract: ADSP-21161 ADSP21261 ADSP-21261
Contextual Info: SHARC Embedded Processor ADSP-21261 a SUMMARY KEY FEATURES High performance 32-bit/40-bit floating-point processor Code compatibility—at assembly level, uses the same instruction set as other SHARC DSPs Single-instruction multiple-data SIMD computational architecture—two 32-bit IEEE floating-point/32-bit fixed-point/

Contextual Info: a SHARC Processor ADSP-21362 Preliminary Technical Data SUMMARY High performance 32-bit/40-bit floating-point processor optimized for high performance automotive audio processing Single-Instruction Multiple-Data SIMD computational architecture On-chip memory—3M bit of on-chip SRAM

Contextual Info: a SHARC Processor ADSP-21365/ADSP-21366 Preliminary Technical Data SUMMARY Single-Instruction Multiple-Data SIMD computational architecture On-chip memory—3M bit of on-chip SRAM and a dedicated 4M bit of on-chip mask-programmable ROM Code compatible with all other members of the SHARC family

AD150

Contextual Info: a SHARC Processor ADSP-21364 Preliminary Technical Data SUMMARY On-chip memory—3M bit of on-chip SRAM and a dedicated 4M bit of on-chip mask-programmable ROM Code compatible with all other members of the SHARC family The ADSP-21364 is available with a 333 MHz core instruction

sharc ADSP-21xxx general block diagram

Abstract: block diagram of ADSP21xxx SHARC processor sharc 21xxx architecture block diagram 4x4 barrel shifter sharc ADSP-21xxx architecture diagram sharc ADSP21xxx architecture ADSP-21160 ADSP-21161 ADSP-21266 JC JB jt
Contextual Info: PRELIMINARY TECHNICAL DATA S a High Performance SHARC Audio Processor ADSP-21266 Preliminary Technical Data SUMMARY High performance 32-bit/40-bit floating point processor optimized for audio processing The ADSP-21266 processes high performance audio while enabling low system costs

spi flash parallel port

Abstract: ADSP-21160 ADSP-21161 ADSP-21262 ADSP-21266 A2388
Contextual Info: SHARC Embedded Processor ADSP-21262 a SUMMARY KEY FEATURES High performance 32-bit/40-bit floating-point processor Code compatibility—at assembly level, uses the same instruction set as other SHARC DSPs Single-instruction multiple-data SIMD computational architecture—two 32-bit IEEE floating-point/32-bit fixed-point/

shift register coding

Abstract: 32-bit shift register shift register ISL5216 AN9987
Contextual Info: IEEE Standard Test Access Port and Boundary Scan Register for the ISL5216 QPDC TM Application Note November 2001 AN9987.1 Russell Davidson & Dejan Radic Introduction: The test access port (TAP) provided on the ISL5216 is compliant with the IEEE Std 1149.1-1990 TAP. The purpose

key board mtm 8 pins

Abstract: BC136 144-Lead LQFP_EP sharc iir filter ADSP-21160 ADSP-21161 ADSP-21362 ADSP-21363 max33 ADSP-21365
Contextual Info: SHARC Processors SUMMARY DEDICATED AUDIO COMPONENTS High performance 32-bit/40-bit floating point processor optimized for high performance audio processing Single-instruction, multiple-data SIMD computational

sis661fx

Abstract: GS1117Y ICS952013 d7677 LM393R hitachi ha md50 sis 963l SRP11 M661MX sis 741gx
Contextual Info: 5 4 3 321 V.1.0 2 Clock Gen. Pentium-M / Celeron-M CPU Sideband Bus RTC,VCC3,VCC5 PAGE 9 1 DC_IN Select PAGE 26 PAGE 30 Thermal D D PAGE 2,3,4 Clock Buffer PAGE 10 ECVCC/+5VAUX 400M/533M PAGE 31 CRT Memory Bus North Bridge PAGE 13 SiS M661GX / FX LVDS Board

F16C20C

Abstract: sd6109 103Z capacitor capacitor 103z 1kv 104k 250v capacitor SD484 kpc817 ZNR2 104Z capacitor 103z
Contextual Info: SD6109 VOLTAGE MODE PWM POWER SUPPLY WITH BUILT-IN SUPERVISOR, PROTECTION AND REGULATION FOR PCs DESCRIPTION The SD6109 is a power management IC for computers. It integrates various monitoring functions and protections, such as AC fail detection, over power protection, negative voltage protection,

Contextual Info: HSP50216 Data Sheet August 17, 2007 Four-Channel Programmable Digital Downconverter FN4557.6 Features • Up to 70MSPS Input The HSP50216 Quad Programmable Digital Downconverter QPDC is designed for high dynamic range applications such as cellular basestations where multiple channel

ME 4946

Contextual Info: ISL5216 TM Data Sheet February 2002 Four-Channel Programmable Digital DownConverter FN6013.1 Features • Up to 95MSPS Input The ISL5216 Quad Programmable Digital DownConverter QPDC is designed for high dynamic range applications such as cellular basestations where multiple channel

dts master audio DL 1200

Abstract: 3x3 bit parallel multiplier 4604 CMOS Dolby prologic ADSP21365 ADSP-21365 CP-1201
Contextual Info: a SHARC Processor ADSP-21365/ADSP-21366 Preliminary Technical Data SUMMARY Single-Instruction Multiple-Data SIMD computational architecture On-chip memory—3M bit of on-chip SRAM and a dedicated 4M bit of on-chip mask-programmable ROM Code compatible with all other members of the SHARC family

Contextual Info: SHARC Processor ADSP-21267 Preliminary Technical Data SUMMARY DAI incorporates two Precision Clock Generators PCG , and an Input Data Port (IDP) that includes a Parallel Data Acquisition Port (PDAP), and three programmable timers, all under software control by the Signal Routing Unit (SRU)

THOMSON-CSF CCD

Abstract: pixel clock generator ttl THOMSOM
Contextual Info: • lOEbû?^ 0002351 TS3 ■ - TH 7993 PIXEL CORRECTOR CIRCUIT DESCRIPTION The TH 7993 operates in association with the memory deli­ vered with the image sensor to manage the pixel defect cor­ rection functions. The correction is made by replacing the signal of the defec­