SCRATCH Search Results

Fairchild TTL

Contextual Info: TTL MEMORY 93435 { 64-BIT LINEAR SELECT READ/WRITE MEMORY FO R M ER LY 9035 TV \ .W d " 'r ^ h “ ^ * " i ig h “ ” ' a 6 4 B " " • « * ' “ ' « • M e m o ry C ell d ,s ,9r.ed l o , use in h.gh speed scratch pad m em ories, it i* a linear select » 6 w o rd b y 4 -b it array.

DS1993

Abstract: DS1992 DS1992L-F5 DS1993L-F5 DS1994 DS1994L-F5 DS9093RA DS9096P DS9101
Contextual Info: D S 1992/D S 1993/D S 1994 A DALLAS W SEM ICONDUCTOR SPECIAL FEATURES • 4096 bits of read/write nonvolatile memory DS1993 and DS1994 • 1024 bits of read/write nonvolatile memory (DS1992) • 256-bit scratchpad ensures integrity of data transfer • Memory partitioned into 256-bit pages for packetizing

101490

Contextual Info: HM101490 Series 65536-Words x 1-Bit Fully Decoded Random Access Memory • DESCRIPTION The HM101490 is ECL 100K compatible, 65536-words by 1-bit read/write random access memory developed for high speed sys­ tems such as scratch pads and control/buffer storage.

Contextual Info: HM101494 Series-16384-Words x 4-Bit Fully Decoded Random Access Memory • DESCRIPTION The HM101494 is ECL 100K compatible, 16384-words by 4-bits read/write random access memory developed for high speed sys­ tems such as scratch pads and control/buffer storage.

HM10414

Abstract: HM10414-1
Contextual Info: H M l 4 1 4 , H M l 4 1 4 - 1 2 5 6 -word x 1-bit Fully Decoded Random Access Memory The HM10414 is E C L 10K com patible, 256-word x 1-bit, read w rite, random access m em ory developed fo r high speed systems such as scratch pad and control/buffer storages.

HM 1211

Abstract: HM2110 HM2110-1 Jj-80
Contextual Info: H M 2 1 1 0 , H M 2 1 1 0 -1 1 0 2 4 - w o rd x 1 - b i t F u lly D e c o d e d R a n d o m A c c e s s M e m o ry The H M 21 10 Series item is an ECL compatible, 1024-word x 1-bit, read/write, random access memory developed for application to scratch pads, control and buffer memories, etc. which require high

75176B

Abstract: COM20019I COM20019I-HD COM20019ILJP COM20020
Contextual Info: COM20019I Low Cost ARCNET ANSI 878.1 Controller with 2K x 8 On-Board RAM Datasheet Product Features Eight, 256 Byte Pages Allow Four Pages TX and RX Plus Scratch-Pad Memory New Features: − Data Rates up to 312.5 Kbps − Programmable Reconfiguration Times

ink cartridge chip

Abstract: AEC-Q100 DS2431 DS2431-A1 DS2431P DS2431X DS2480B P1451 polynomial TSOC 6
Contextual Info: 19-4675; Rev 10; 3/11 1024-Bit, 1-Wire EEPROM The DS2431 is a 1024-bit, 1-Wire EEPROM chip organized as four memory pages of 256 bits each. Data is written to an 8-byte scratchpad, verified, and then copied to the EEPROM memory. As a special feature, the

DS1973

Abstract: DS1973-F3 DS1973-F5 DS2433 DS9092 DS9093A DS9093RA DS9096P DS9101 Maxim date code
Contextual Info: 19-4889; Rev 8/09 DS1973 4Kb EEPROM iButton SPECIAL FEATURES COMMON iButton FEATURES • •       4096 bits Electrically Erasable Programmable Read Only Memory EEPROM Overdrive mode boosts communication speed to 142kbps 256-bit scratchpad ensures integrity of data

COM20019I

Abstract: COM20019I-DZD COM20019I-HD COM20019I-HT COM20019ILJP
Contextual Info: COM20019I Low Cost ARCNET ANSI 878.1 Controller with 2K x 8 On-Board RAM Datasheet Product Features ƒ New Features: ƒ − Data Rates up to 312.5 Kbps − Programmable Reconfiguration Times Eight, 256 Byte Pages Allow Four Pages TX and RX Plus Scratch-Pad Memory

Contextual Info: 13 10 'nDrrnDrTTiDrrnDq NOTES; 1. MATERIALS: HOUSING - VECTRA A -1 30, 9 4 V -0 , BLACK TERMINAL - PHOS. BRONZE ALLOY 5 2 1. 2. ) 8 CKT. SHOWN FOR ILLUSTRATION PURPOSES. SEE CHART ON SHEET 7 FOR OTHER SIZES. 3. ) SCRATCHES AND BURNISHING ALLOWED ON TERMINAL TA ILS PROVIDING BASE METAL

Contextual Info: II 12 IS 9 T 8 6 1 71979 3 1 2 NOTES; .100 2.54) nuim uim uim ur7i 0 0 □B .260 (6.60) 8 CKT. SHOWN FOR ILLUSTR ATIO N PURPOSES SEE CHART ON SHEET 8 FOR OTHER SIZES, 3. ) SCRATCHES AND BURNISHING ALLOWED ON TERMINAL T A ILS PROVIDING BASE METAL IS NOT EXPOSED.

diode G4010

Abstract: ds1302 circuit real time clock Register definitio super cap 5.5v ds1302 block diagram ds1302 circuit ds1302 circuit diagram G4010 DS1202 DS1302 DS1302S
Contextual Info: DS1302 DS1302 Trickle Charge Timekeeping Chip FEATURES PIN ASSIGNMENT • Real time clock counts seconds, minutes, hours, date of the month, month, day of the week, and year with leap year compensation valid up to 2100 • 31 x 8 RAM for scratchpad data storage

iButton Chips

Abstract: DS9092 DS1995 DS1996 DS9093F DS9093RA DS9101 UL913
Contextual Info: DS1995 DS1995 16Kbit Memory iButtonTM F5 MICROCANTM SPECIAL FEATURES • 16384 bits of read/write nonvolatile memory • 256–bit scratchpad ensures integrity of data transfer • Overdrive mode boosts communication to 142k bits 5.89 0.36 0.51 per second

Contextual Info: PRODUCT PREVIEW DALLAS ! SEMICONDUCTOR FEATURES DS87C550 EPROM High-Speed Micro with A/D and PWM PIN ASSIGNMENT • 87C52-Compatible 61 8051 pin- and instruction set-compatible Three 16-bit timer/counters 256 bytes scratchpad RAM ■ ■ On-chip Memory 8 kbytes EPROM OTP & Windowed Packages

Contextual Info: ECL 4096-BIT BIPOLAR RANDOM ACCESS MEMORY F U JIT S U 4 0 9 6 -B IT B IP O L A R EC L R A N D O M ACCESS M E M O R Y T he F u jits u M BM 1 0 4 7 4 A is f u lly decoded 4 0 9 6 -b it E C L re a d /w rite random access m e m o ry designed fo r high-speed scratch pad, c o n tro l and b u ffe r storage

Contextual Info: _ _ CY10E470 CY100E470 s i CYPRESS ^S W SEMICONDUCTOR . 4K x l E C L Features Functional Description • 4096 x 1—bit organization • High speed/low power tAA —5 ns T h e Cypress CY 10E470 an d CY 100E470 are E C L R A M s designed fo r scratch pad,

Contextual Info: FUJITSU ECL 16384-BIT BIPOLAR RANDOM ACCESS MEMORY MBM10484AAugust 1988 Edition 2.0 16384-BIT BIPOLAR ECL RANDOM ACCESS M EM ORY The Fujitsu MBM 10484A is fu lly decoded 16384-bit ECL read/write random access memory designed fo r high-speed scratch pad, control and buffe r storage

p5cn

Contextual Info: “ DS80C390 Dual CAN High-Speed Microprocessor m m c o m m c tm PIN ASSIGNMENT FEATURES • 80C52 compatible - 8051 instruction-set compatible - Five 8-bit I/O ports - Three 16-bit timer/counters - 256 bytes scratchpad RAM ■ High-Speed Architecture - 4 clocks/machine cycle 8051=12

MIPS64

Abstract: RM9220
Contextual Info: RM9220 Released 54 4: :3 05 04 • Supports 25.6 Gbps memory. • Supports DDR SDRAM options. • Supports 2 Gbytes using 512 Mbit SDRAM and 4 Gbytes using 1 Gbit SDRAM. ADDITIONAL FEATURES • Provides 8 Kbytes integrated low latency scratch RAM. • Provides an integrated on-chip EJTAG

PM8393

Abstract: 4 channel pwm transmitter receiver Logic Card of PA fan "tape storage" AT/PM8393
Contextual Info: PM8393 SMC Preliminary Storage Management Controller PM 01 05 20 t, us ug 8A ay nd Mo n co In rtm Pa PM8393 SMC 128K Scratch RAM /w Parity FC Interface Peripheral Subsystem Memory I/F Mux of Memory Controller MultimasterTw MultimasterTw o Wire Interface o Wire Interface

HYC9088

Abstract: COM20020I COM20020I3V-HD COM20020ILJP3V COM20020IP3V RG62 NDS322
Contextual Info: COM20020I 3.3V COM20020I 3.3V ULANC Universal Local Area Network Controller with 2K x 8 On-Board RAM FEATURES New Features Eight, 256 Byte Pages Allow Four Pages TX and RX Plus Scratch-Pad Memory - Data Rates up to 5 Mbps - Programmable Reconfiguration Times

CD40108

Abstract: 751E MC14580B MC14XXXBCL MC14XXXBCP MC14XXXBDW
Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA MC14580B 4 x 4 Multiport Register L SUFFIX CERAMIC CASE 623 The MC14580B is a 4 by 4 multiport register useful in small scratch pad memories, arithmetic operations when coupled with an adder, and other data storage applications. It allows independent reading of any two words or the

Contextual Info: DS2430 PRELIM INARY DALLAS DS2430 s e m ic o n d u c t o r 2 5 6 —Bit S h s d o w R A M with 6 4 —Bit ID PIN ASSIGNMENT FEATURES • 256 bits of scratchpad SRAM memory (one 32 byte page) DQ GND • 256 bits of non-volatile EEPROM user memory avail­