SCATTER-GATHER EXAMPLE Search Results

P2S3

Abstract: SGDA DS440 Scatter-Gather
Contextual Info: DS440 April 24, 2009 Channelized Direct Memory Access and Scatter Gather v1.00a Product Specification Introduction LogiCORE IP Facts This specification is for a DMA Scatter Gather controller which can scale up to a relatively large number of channels (hundreds). Many concepts from

Scatter-Gather direct memory access SG-DMA

Abstract: memory access (DMA) controller Scatter-Gather CRC-32 QII55003-7 constructs
Contextual Info: 5. Scatter-Gather DMA Controller Core QII55003-7.1.0 Core Overview The Scatter-Gather direct memory access SG-DMA controller core implements high-speed data transfer between two devices. The SG-DMA core can be used to transfer data from: • ■ ■ memory to memory

LFE3-95EA-7FN672CES

Abstract: Scatter-Gather wishbone interface wishbone HB1009 modelsim SE 6.3f user guide IPUG67
Contextual Info: Scatter-Gather Direct Memory Access Controller IP Core User’s Guide October 2010 IPUG67_01.6 Table of Contents Chapter 1. Introduction . 4

Scatter-Gather example

Abstract: Scatter-Gather
Contextual Info: Accelerating Functions with the C2H Compiler: Scatter-Gather DMA with Checksum July 2006, Version 1.1 Application Note 417 Introduction The Nios II C-to-Hardware Acceleration C2H Compiler is a powerful tool that generates hardware accelerators for software functions. This application note uses the C2H Compiler to map C code for a scatter-gather direct

Contextual Info: Preliminary PowerPC 405CR Embedded Controller Data Sheet Features • PowerPCTM 405 32-bit RISC processor core operating up to 200 MHz • DMA support for external peripherals, internal UART and memory - Memory Management Unit - Scatter-gather chaining supported

TS6 v14

Contextual Info: Preliminary PowerPC 405CR Embedded Controller Data Sheet Features • IBM PowerPCTM 405 32-bit RISC processor core operating up to 266MHz • DMA support for external peripherals, internal UART and memory - Memory Management Unit - Scatter-gather chaining supported

TS6 v14

Abstract: 405CR frequency-266MHz
Contextual Info: Preliminary PowerPC 405CR Embedded Controller Data Sheet Features • IBM PowerPCTM 405 32-bit RISC processor core operating up to 266MHz • DMA support for external peripherals, internal UART and memory - Memory Management Unit - Scatter-gather chaining supported

4413C

Contextual Info: LAN9420/LAN9420i Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface PRODUCT FEATURES Datasheet Highlights „ „ „ „ „ „ „ Optimized for embedded applications with 32-bit RISC CPUs Integrated descriptor based scatter-gather DMA and

Contextual Info: LAN9420/LAN9420i Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface PRODUCT FEATURES Datasheet Highlights „ „ „ „ „ „ „ Optimized for embedded applications with 32-bit RISC CPUs Integrated descriptor based scatter-gather DMA and

LAN9420

Abstract: 128-PIN CRC-16 IEC61249-2-21
Contextual Info: LAN9420/LAN9420i Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface PRODUCT FEATURES Datasheet Highlights „ „ „ „ „ „ „ Optimized for embedded applications with 32-bit RISC CPUs Integrated descriptor based scatter-gather DMA and

BA1 K19

Abstract: BA1K19 IBM25PPC405CR-3BC200C PPC405CR PowerPC EBC 405CR PPC405 SA-12E PowerPC 405CR PPC405 IBM
Contextual Info: PowerPC 405CR Embedded Processor Data Sheet Features • IBM PowerPC 405 32-bit RISC processor core operating up to 266MHz - Memory Management Unit - 16KB instruction and 8KB data caches - Scatter-gather chaining supported - Four channels • Programmable Interrupt Controller supports

100n x2 pme 285 mb

Abstract: IP100A IP100ALF 2N2905 transistor 100BASE-FX 100N 93C46 0090C3 TFD65 "network interface cards"
Contextual Info: IP100A LF Preliminary Data Sheet Integrated 10/100 Ethernet MAC + PHY Features General Description Single chip 10/100BASE, half or full duplex Ethernet Media Access Controller IEEE 802.3 compliant 100BASE-TX/100BASE-FX/10BASE-T PCI Bus master scatter/gather DMA on any

LAN9420

Abstract: LAN9420i EPC TRANSFORMER 128-PIN AD10 CRC-16 jumbo led
Contextual Info: LAN9420/LAN9420i Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface PRODUCT FEATURES Datasheet Highlights „ „ „ „ „ „ „ Optimized for embedded applications with 32-bit RISC CPUs Integrated descriptor based scatter-gather DMA and

TS6 v14

Abstract: IBM CoreConnect bus
Contextual Info: PowerPC 405CR Embedded Processor Data Sheet Features • IBM PowerPC 405 32-bit RISC processor core operating up to 266MHz - Memory Management Unit - 16KB instruction and 8KB data caches - Scatter-gather chaining supported - Four channels • Programmable Interrupt Controller supports

IBM25PPC405CR-3BC200C

Abstract: RISCwatch Trace IBM J9 405CR PC-100 PPC405 PPC405CR SA12E ppc405 BSDL
Contextual Info: PowerPC 405CR Embedded Controller Data Sheet Features • IBM PowerPCTM 405 32-bit RISC processor core operating up to 266MHz • DMA support for external peripherals, internal UART and memory - Memory Management Unit - Scatter-gather chaining supported - 16KB instruction and 8KB data caches

ppc405 BSDL

Contextual Info: PowerPC 405CR Embedded Controller Data Sheet Features • IBM PowerPCTM 405 32-bit RISC processor core operating up to 266MHz • DMA support for external peripherals, internal UART and memory - Memory Management Unit - Scatter-gather chaining supported - 16KB instruction and 8KB data caches

communication between cpu and iop

Abstract: RISCwatch schema SCHEMAT 480R 480RDK bus arbiter "network interface cards"
Contextual Info: IOP 480 Features • PowerPC 32-Bit RISC CPU Core with MMU, 4KB I-Cache and 2KB D-Cache v2.2 Compliant 32-Bit 33MHz Controller with Two Block Mode or Scatter/Gather DMA Channels which allow unlimited bursts up to 132Mbytes/Second Processor ■ PCI ■ CompactPCI

communication between cpu and iop

Abstract: low cost processor PLX 480 Programmable interval timer chips "network interface cards"
Contextual Info: IOP 480 Highlights • PowerPC 32-Bit RISC CPU Core with MMU, 4KB I-Cache and 2KB D-Cache ■ Performance up to 70 MIPS @ 66MHz ■ PCI v2.2 Compliant 32-Bit 33MHz Controller with Two Block Mode or Scatter/Gather DMA Channels which allow unlimited bursts up to

CRC-10

Abstract: MXT3010
Contextual Info: Planning for, and upgrading to, the MXT3020C Applications Note #18 Revision 3.0 - 14 July 1998 Order Number: 100388-03 Maker Communications 73 Mount Wayte Avenue Framingham, MA 01702 April 1998 Copyright c 1998 by Maker Communications, Inc. All rights reserved.

semiconductor manual reference

Abstract: gather capacitor MXT3010 DECchip 21140 FTC 380 manual R50BC MOVER+592.+T.+X1.+00
Contextual Info: MXT3020 reference manual version 2.0 Order Number: 100107-02 Revision B of the MXT3020 November 1997 Copyright c 1997 by Maker Communications, Inc. All rights reserved. Printed in the United States of America. The information in this document is believed to be correct, however, the

TC6367

Abstract: CRC-10 MXT3010 MXT4400 486 motherboard schematic AS3010
Contextual Info: MXT3020 reference manual version 4.0 Order Number: 100107-04 Revision C of the MXT3020 July 1999 Copyright c 1999 by Maker Communications, Inc. All rights reserved. Printed in the United States of America. The information in this document is believed to be correct, however, the

fpga cdma ip vhdl examples

Abstract: DS792 AMBA AXI4 stream specifications xc6vlx240t XPS Central DMA cdma system implementation fpga cdma by vhdl examples
Contextual Info: LogiCORE IP AXI Central Direct Memory Access v3.02.a DS792 January 18, 2012 Product Specification Introduction LogiCORE IP Facts Table The Advanced eXtensible Interface Central Direct Memory Access (AXI CDMA) core is a soft Xilinx Intellectual Property (IP) core for use with the Xilinx

an3396

Abstract: MPC5500 Configuration and Initialization MPC5534 AN2864SW eMIOS channel is set up to drive the eTPU decimation MPC500 MPC5500 MPC5561 mpc5500r19
Contextual Info: Freescale Semiconductor Application Note Document Number: AN3396 Rev. 0, 01/2007 MPC5500: A Decimation Solution with Zero CPU Loading by: Geoff Emerson David McMenamin MCD Applications East Kilbride, Scotland 1 Introduction The MPC5500 microcontroller family provides a

an3396

Abstract: MPC500 MPC5500 MPC5534 MPC5561 MPC5500 Configuration and Initialization eMIOS channel is set up to drive the eTPU emios
Contextual Info: Freescale Semiconductor Application Note MPC5500: A Decimation Solution with Zero CPU Loading by: Geoff Emerson David McMenamin MCD Applications East Kilbride, Scotland 1 Introduction The MPC5500 microcontroller family provides a flexible feature set enabling a wide range of automotive