SCAS682 Search Results

SCAS682 Datasheets Context Search

Catalog Datasheet	Type	Document Tags	PDF
CDC5801 Abstract: CDCVF2310 Contextual Info: CDC5801 LOW JITTER CLOCK MULTIPLIER AND DIVIDER WITH PROGRAMMABLE DELAY AND PHASE ALIGNMENT SCAS682A – OCTOBER 2002 D Low Jitter Clock Multiplier by x4, x6, x8. D D D D D D D D D D D Input Frequency Range 19 MHz to 125 MHz . Supports Output Frequency From 150 MHz to 500 MHz	Original	cdc5801 scas682a cdcvf2310	PDF
12K-20MHZ Contextual Info: SCAS682 • • • CDC5801 LOW JITTER CLOCK MULTIPLIER & DIVIDER WITH PROGRAMMABLE DELAY AND PHASE ALIGNMENT Low jitter clock multiplier by X4, X6, X8. Input frequency range 19MHZ to 135MHZ . Supports output frequency from 76 MHZ to 540MHZ Low jitter clock divider by /2, /3, /4. Input frequency range	Original	scas682 cdc5801 19mhz 135mhz +6540mhz 75mhz 130mhz 25mhz 65mhz 12k-20mhz	PDF
CDC5801 Abstract: CDC5801DBQ CDC5801DBQR CDC5801DBQRG4 CDCVF2310 Contextual Info: CDC5801 LOW JITTER CLOCK MULTIPLIER AND DIVIDER WITH PROGRAMMABLE DELAY AND PHASE ALIGNMENT SCAS682B − OCTOBER 2002 − OCTOBER 2005 D Low Jitter Clock Multiplier by x4, x6, x8. D D D D D D D D D D D Input Frequency Range 19 MHz to 125 MHz . Supports Output Frequency	Original	cdc5801 scas682b cdc5801dbq cdc5801dbqr +2cdc5801dbqrg4 cdcvf2310	PDF
AT 2005A Abstract: CDF5801 FPGA reference DCF58 TLK2521 CDC7005 CDCF5801 CDCV304 CDCVF2310 DCF5801 Contextual Info: Application Report SCAA070B – January 2004 – Revised October 2005 A General Guideline: How to Use the CDCF5801 for Phase Alignment/Adjustment Firoj Kabir. CDC/HPA	Original	scaa070b cdcf5801 at 2005a cdf5801 +7fpga reference dcf58 tlk2521 cdc7005 cdcv304 cdcvf2310 dcf5801	PDF