SCAS627 Search Results

Contextual Info: CDC857-2, CDC857-3 2.5-/3.3-V PHASE-LOCK LOOP CLOCK DRIVERS SCAS627A – SEPTEMBER 1999 – DECEMBER 1999 D D D D D D Phase-Lock Loop Clock Distribution for Double Data Rate Synchronous DRAM Applications Distributes One Differential Clock Input to Ten Differential Outputs

Contextual Info: CDC857-3 3.3-/2.5-V PHASE-LOCK LOOP CLOCK DRIVER SCAS627 – SEPTEMBER 1999 D D D D D D Phase-Lock Loop Clock Distribution for Double Data Rate Synchronous DRAM Applications Distributes One Differential Clock Input to Ten Differential Outputs External Feedback Pins FBIN, FBIN Are

CDC857

Abstract: CDC857-2 CDC857-3
Contextual Info: CDC857-2, CDC857-3 2.5-/3.3-V PHASE-LOCK LOOP CLOCK DRIVERS SCAS627A – SEPTEMBER 1999 – DECEMBER 1999 D D D D D D Phase-Lock Loop Clock Distribution for Double Data Rate Synchronous DRAM Applications Distributes One Differential Clock Input to Ten Differential Outputs

CDC857

Abstract: CDC857-2 CDC857-2DGGR CDC857-3
Contextual Info: CDC857-2, CDC857-3 2.5-/3.3-V PHASE-LOCK LOOP CLOCK DRIVERS SCAS627A – SEPTEMBER 1999 – DECEMBER 1999 D D D D D D Phase-Lock Loop Clock Distribution for Double Data Rate Synchronous DRAM Applications Distributes One Differential Clock Input to Ten Differential Outputs