SCAS614 Search Results

SCAS614 Datasheets Context Search

Catalog Datasheet	Type	Document Tags	PDF
48-PIN Abstract: CDC318A CDC318ADL CDC318ADLG4 Contextual Info: CDC318A 1-LINE TO 18-LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS614A – SEPTEMBER 1998 – REVISED JUNE 2002 D D D D D D D D D D DL PACKAGE TOP VIEW High-Speed, Low-Skew 1-to-18 Clock Buffer for Synchronous DRAM (SDRAM) Clock Buffering Applications	Original	cdc318a 18-line scas614a 1-to-18 +5100-mhz mil-std-883 48-pin cdc318adl cdc318adlg4	PDF
48-PIN Abstract: CDC318A CDC318ADL CDC318ADLG4 CDC318ADLR Contextual Info: CDC318A 1ĆLINE TO 18ĆLINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS614A − SEPTEMBER 1998 − REVISED JUNE 2002 D High-Speed, Low-Skew 1-to-18 Clock Buffer D D D D D D D D D DL PACKAGE TOP VIEW for Synchronous DRAM (SDRAM) Clock Buffering Applications	Original	cdc318a 18line scas614a 1-to-18 +6100-mhz mil-std-883 48-pin cdc318adl cdc318adlg4 cdc318adlr	PDF
K3638 Abstract: 4Y04 Contextual Info: CDC318A 1-LINE TO 18-LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS614A – SEPTEMBER 1998 – REVISED JUNE 2002 D D D D D D D D D D DL PACKAGE TOP VIEW High-Speed, Low-Skew 1-to-18 Clock Buffer for Synchronous DRAM (SDRAM) Clock Buffering Applications	Original	cdc318a 18-line scas614a 1-to-18 +5100-mhz mil-std-883 48-pin k3638 4y04	PDF
48-PIN Abstract: CDC318A Contextual Info: CDC318A 1ĆLINE TO 18ĆLINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS614A − SEPTEMBER 1998 − REVISED JUNE 2002 D High-Speed, Low-Skew 1-to-18 Clock Buffer D D D D D D D D D DL PACKAGE TOP VIEW for Synchronous DRAM (SDRAM) Clock Buffering Applications	Original	cdc318a 18line scas614a 1-to-18 +3100-mhz mil-std-883 48-pin	PDF
k3638 Contextual Info: CDC318A 1-LINE TO 18-LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS614A – SEPTEMBER 1998 – REVISED JUNE 2002 D D D D D D D D D D DL PACKAGE TOP VIEW High-Speed, Low-Skew 1-to-18 Clock Buffer for Synchronous DRAM (SDRAM) Clock Buffering Applications	Original	cdc318a 18-line scas614a 1-to-18 +4100-mhz mil-std-883 48-pin k3638	PDF
Contextual Info: CDC318A 1ĆLINE TO 18ĆLINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS614A − SEPTEMBER 1998 − REVISED JUNE 2002 D High-Speed, Low-Skew 1-to-18 Clock Buffer D D D D D D D D D DL PACKAGE TOP VIEW for Synchronous DRAM (SDRAM) Clock Buffering Applications	Original	cdc318a scas614a 1-to-18 100-mhz +2mil-std-883 48-pin	PDF
CDC318A Contextual Info: CDC318A 1-LINE TO 18-LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS614 – SEPTEMBER 1998 D D D D D D D D D D DL PACKAGE TOP VIEW High-Speed, Low-Skew 1-to-18 Clock Buffer for Synchronous DRAM (SDRAM) Clock Buffering Applications Output Skew, tsk(o), Less Than 250 ps	Original	cdc318a 18-line scas614 1-to-18 +3100-mhz mil-std-883 48-pin	PDF
48-PIN Abstract: CDC318A Contextual Info: CDC318A 1-LINE TO 18-LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS614A – SEPTEMBER 1998 – REVISED JUNE 2002 D D D D D D D D D D DL PACKAGE TOP VIEW High-Speed, Low-Skew 1-to-18 Clock Buffer for Synchronous DRAM (SDRAM) Clock Buffering Applications	Original	cdc318a 18-line scas614a 1-to-18 +3100-mhz mil-std-883 48-pin	PDF
48-PIN Abstract: CDC318A Contextual Info: CDC318A 1-LINE TO 18-LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS614A – SEPTEMBER 1998 – REVISED JUNE 2002 D D D D D D D D D D DL PACKAGE TOP VIEW High-Speed, Low-Skew 1-to-18 Clock Buffer for Synchronous DRAM (SDRAM) Clock Buffering Applications	Original	cdc318a 18-line scas614a 1-to-18 +3100-mhz mil-std-883 48-pin	PDF
Contextual Info: CDC318A 1ĆLINE TO 18ĆLINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS614A − SEPTEMBER 1998 − REVISED JUNE 2002 D High-Speed, Low-Skew 1-to-18 Clock Buffer D D D D D D D D D DL PACKAGE TOP VIEW for Synchronous DRAM (SDRAM) Clock Buffering Applications	Original	cdc318a 18line scas614a 1-to-18 +3100-mhz mil-std-883 48-pin	PDF