SA 2003 IC Search Results

EM6323

Abstract: EM6324 em microelectronic
Contextual Info: EM MICROELECTRONIC - MARIN SA EM6323/24 Reset Circuit with Manual Reset and Watchdog Description Features The EM6323/24 are low power, high precision reset ICs featuring a manual reset and a watchdog inputs. They have different threshold voltages and several timeout reset periods

MCP002-0A

Abstract: 100100XXX IC71V08F32AS04-85B
Contextual Info: IC71V08F32xS04 IC71V16F32xS04 Document Title 3.0 Volt-Only Flash & SRAM COMBO with Stacked Multi-Chip Package MCP - 32 Mbit Simultaneous Operation Flash Memory and 4 Mbit Static RAM Revision History Revision No History Draft Date Remark 0A Initial Draft

EM4050

Abstract: H4002 125 kHz RFID READER EM 18 CIRCUIT 125 kHz RFID EM em h4002 H4002 rfid biphase encoder 125 kHz RFID EM 18 rfid manchester ISO-11785
Contextual Info: EM MICROELECTRONIC - MARIN SA EM4469 512 bit Read/Write Contactless Identification Device Description Features EM4469 is a CMOS integrated circuit intended for use in electronic Read/Write RF transponders. § § § § § § The IC is powered by picking the energy from a

Transistor 5C5

Contextual Info: IC71V08F32xS08 IC71V16F32xS08 Document Title 3.0 Volt-Only Flash & SRAM COMBO with Stacked Multi-Chip Package MCP - 32 Mbit Simultaneous Operation Flash Memory and 8 Mbit Static RAM Revision History Revision No History Draft Date 0A 0B Initial Draft Add 73 ball BGA package

EMTG48

Contextual Info: EM MICROELECTRONIC - MARIN SA Theseus Gold 48 EMTG48 48kB FLASH Memory Smart Card IC Environment Single 3.0V to 5.0V supply ± 10% -25 to +85 C operating temperature Max supply current 10mA > 4 kV ESD Protection HBM CPU Software compatible CMOS 8051 industry standard

ISO7816-3 T1

Abstract: ISO7816-3 EMTG96-3G iso 7816-3 ISO-7816-3 ISO78163 "JAVA CARD"
Contextual Info: EM MICROELECTRONIC - MARIN SA Theseus Gold 96 3G EMTG96-3G 96kB FLASH Memory Smart Card IC Environment Single 3.0V to 5.0V supply ± 10% -25 to +85 C operating temperature Max supply current 10mA > 4 kV ESD Protection HBM CPU Software compatible CMOS 8051 industry standard

Contextual Info: IC62LV51216L IC62LV51216LL Document Title 512 K x 16 bit Low Voltage and Ultra Low Power CMOS Static RAM Revision History Revision No History Draft Date 0A 0B Initial Draft January 3,2002 1. Add CE2 pin for 48 pin TF-BGA September 2,2002 2. Change for ICC: 35 mA to 30 mA for 55 ns Industrial product

ta 8659 n

Abstract: ta 8659 an TA 8659 HT8658A lf 8659 m386 ta 8659a n HT8658 HT8659
Contextual Info: HOLTEK r r HT8658/HT8659 Voice Recorder DRAM Features • • • • • O p e ra tin g v o lta g e : 4 .5 V ~ 5 .5 V A D M coding a lg o rith m D R A M op tion s: - 256x4-b it - lM x 3 -b it B u ilt-in 2 -sta g e M IC a m p lifie r B u ilt-in low p a s s filte r

AD133

Abstract: AD1334
Contextual Info: A N A LO G D E V IC E S Four-Channel 12-Bit Sampling A/D Converter for Digital Signal Processing ADI334 1.1 Scope. This specification covers the detail requirements for a hybrid, 12-bit analog-to-digital converter including quad sample-and-hold, multiplexer, reference, timing circuitry and F IF O memory.

IC63LV1024-8BI

Contextual Info: IC63LV1024 Document Title 128K x 8 Hight Speed SRAM with 3.3V Central Power Revision History Revision No History Draft Date 0A 0B Initial Draft Add B 36-pin TF-BGA 6x8mm and H (32-pin TSOP-1 8x13.4mm) package type To correct the TYPO error September 12,2001

S5000PSLSAS

Abstract: D16310-701 S5000XVN E11027-101 9650SE-8LPML S5000PSLSATAR SROMBSAS18E ati x1600 D25296-301 EXPI9300PT
Contextual Info: Intel Server Boards S5000PSL/S5000XSL, Intel® Workstation Board ® S5000XVN, and Intel Server System SC5400RA Tested Hardware and Operating System List Revision 2.9 December 2008 Enterprise Platforms and Services Division Disclaimers Intel® Server Boards S5000PSL/S5000XSL, Intel® Workstation Board

32K x 8 HIGH SPEED CMOS STATIC RAM

Abstract: IC61LV256-12JG
Contextual Info: IC61LV256 Document Title 32K x 8 Hight Speed SRAM with 3.3V Revision History Revision No History Draft Date 0A 0B Initial Draft Add Pb-free parts April 19,2002 November 28,2003 Remark The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and

GT1 X02

Abstract: SiS chipset 486 82c681 ram 2112 SIS chipset for 486 opti 486 chipset 82C631 80487SX HD3112 sd338
Contextual Info: i »9? OPTÎ-386/486WB EISA Chipset 82C681/82C682/82C686/82C687 EBC/MCC/ISP/DBC D A T A B O O K Preliminary Version 1.3 / Powered by ICminer.com Electronic-Library Service CopyRight 2003 OPTÏ-386/486WB EISA DATABOOK PRELIMINARY Version 1.3 Disclaimer This specification is subject to change without notice. OPTi, Incorporated assumes no

CXK77N18B160GB-3

Abstract: CXK77N36B160GB-3 CXK77N36B160GB-33 CXK77N36B160GB-4 BGA-119
Contextual Info: SONY  CXK77N36B160GB / CXK77N18B160GB 16Mb LW LS R-R HSTL High Speed Synchronous SRAM 512K x 36 or 1M x 18 3/33/4 Preliminary Description The CXK77N36B160GB (organized as 524,288 words by 36 bits) and the CXK77N18B160GB (organized as 1,048,576 words by 18 bits) are high speed CMOS synchronous static RAMs with common I/O pins. These synchronous SRAMs integrate input

10D-11

Abstract: K7R160982B K7R160982B-FC16 K7R160982B-FC20 K7R161882B K7R161882B-FC16 K7R161882B-FC20 K7R163682B K7R163682B-FC16 K7R163682B-FC20
Contextual Info: K7R163682B K7R161882B K7R160982B 512Kx36 & 1Mx18 & 2Mx9 QDR TM II b2 SRAM Document Title 512Kx36-bit, 1Mx18-bit, 2Mx9-bit QDRTM II b2 SRAM Revision History History Draft Date Remark 0.0 1. Initial document. Oct. 17, 2002 Advance 0.1 1. Change the Boundary scan exit order.

A1049

Abstract: TRANSISTOR A1049 2SC2459 A1049 transistor
Contextual Info: 2 SA 1049 TO SH IB A 2 S A 1 049 TOSHIBA TRANSISTOR SILICON PNP EPITAXIAL TYPE PCT PROCESS AUDIO FREQUENCY AM PLIFIER APPLICATIONS Small Package. High Breakdown Voltage : V0EO = —120V (Min.) High hpE : hjnE = 200~700 Excellent hpg Linearity : hpE (IC= -0.1m A )/h p E (I(]= -2m A ) = 0.95 (Typ.)

Contextual Info: EN29LV040A Purpose Eon Silicon Solution Inc. hereinafter called “Eon” is going to provide its products’ top marking on ICs with < cFeon > from January 1st, 2009, and without any change of the part number and the compositions of the ICs. Eon is still keeping the promise of quality for all the products with the

Contextual Info: K7R163682B K7R161882B K7R160982B K7R160882B Preliminary 512Kx36 & 1Mx18 & 2Mx9 & 2Mx8 QDR TM II b2 SRAM Document Title 512Kx36-bit, 1Mx18-bit, 2Mx9-bit, 2Mx8-bit QDR TM II b2 SRAM Revision History History Draft Date Remark 0.0 1. Initial document. Oct. 17, 2002

Contextual Info: K7R163684B K7R161884B 512Kx36 & 1Mx18 QDR TM II b4 SRAM Document Title 512Kx36-bit,1Mx18-bit QDRTM II b4 SRAM Revision History History Draft Date Remark 0.0 1. Initial document. Oct. 17. 2002 Advance 0.1 1. Change the Boundary scan exit order. 2. Correct the Overshoot and Undershoot timing diagram.

Contextual Info: K7I163684B K7I161884B K7I160884B Preliminary 512Kx36 & 1Mx18 & 2Mx8 DDRII CIO b4 SRAM Document Title 512Kx36-bit, 1Mx18-bit, 2Mx8-bit DDRII CIO b4 SRAM Revision History Rev. No. History Draft Date Remark 0.0 1. Initial document. Dec. 16, 2002 Advance 0.1 2. Add the speed bin -25

Contextual Info: K7R323682M K7R321882M K7R320982M K7R320882M 1Mx36 & 2Mx18 & 4Mx9 & 4Mx8 QDRTM II b2 SRAM Document Title 1Mx36-bit, 2Mx18-bit, 4Mx9-bit, 4Mx8-bit QDR TM II b2 SRAM Revision History History Draft Date Remark 0.0 1. Initial document. June, 30 2001 Advance 0.1

K7I161882B-FC25

Abstract: K7I161882B-FC30 K7I163682B K7I163682B-FC16 K7I163682B-FC20 K7I163682B-FC25 K7I163682B-FC30 IR 10e 1c
Contextual Info: K7I163682B K7I161882B K7I160882B Premilinary 512Kx36 & 1Mx18 & 2Mx8 DDRII CIO b2 SRAM Document Title 512Kx36-bit, 1Mx18-bit, 2Mx8-bit DDRII CIO b2 SRAM Revision History Rev. No. History Draft Date Remark 0.0 1. Initial document. Oct. 23. 2002 Advance 0.1 1. Add the speed bin -33, -30

K7R161884B

Abstract: K7R161884B-FC25 K7R161884B-FC30 K7R163684B K7R163684B-FC16 K7R163684B-FC20 K7R163684B-FC25 K7R163684B-FC30
Contextual Info: K7R163684B K7R161884B K7R160884B Preliminary 512Kx36 & 1Mx18 & 2Mx8 QDR TM II b4 SRAM Document Title 512Kx36-bit,1Mx18-bit, 2Mx8-bit QDR TM II b4 SRAM Revision History History Draft Date Remark 0.0 1. Initial document. Oct. 17. 2002 Advance 0.1 1. Change the Boundary scan exit order.

Contextual Info: K7I323682M K7I321882M K7I320882M 1Mx36 & 2Mx18 & 4Mx8 DDRII CIO b2 SRAM Document Title 1Mx36-bit, 2Mx18-bit, 4Mx8-bit DDRII CIO b2 SRAM Revision History Rev. No. History Draft Date Remark 0.0 1. Initial document. October, 22 2001 Advance 0.1 1. 2. 3. 4. 5.