S8820 Search Results

88LS120

Abstract: 78ls12
Contextual Info: Semiconductor DS78LS120/DS88LS120 Dual Differential Line Receiver Noise Filtering and Fail-Safe General Description Input specifications meet or exceed those of the popular D S7820/D S8820 line receiver. The D S78LS120 and D S88LS120 are high perform ance,

Contextual Info: Semiconductor DS78C20/DS88C20 Dual CMOS Compatible Differential Line Receiver Features • Meets requirem ents of EIA S tandards RS-232-C RS-422 and RS-423, and Federal Standards 1020 and 1030 Input specifications m eet o r exceed those of the popular D S7820/D S8820 line receiver, and the pinout is identical.

S3691

Contextual Info: + M ay 1998 & National Semiconductor D / ^1 oo O N> DS78C120/DS88C120 Dual CMOS Compatible Differential Line Receiver O (/) oo oo General Description Features The D S78C 120 and D S88C 120 are high perform ance, dual differential, C M O S com patible line receivers for both bal­

MDM 6600

Abstract: mt 1389 de 2061 D nikko AR9344 bosch AL 1115 CV denso alternator 7805/3A bosch al 1450 dv CATERPILLAR 207-1560 ba 4918
Contextual Info: No. 9800-OERF-007 Replaces • Remplace • Substituye No. 9800-OERF-005 Dixie Electric Ltd. OEM CROSS REFERENCE GUIDE DE RÉFÉRENCE GUÍA DE REFERENCIA 2007 Index • Índice AGCO .1

74ls314

Abstract: SN75450BN RM741DC 74LS208 MC1711G 74s214 SN75361AP 74LS207 RS 75491 MC1741L
Contextual Info: PRODUCT RANGE PAGE M IC R O P R O C E S S O R S 2-21 M E M O R IE S MOS M IC R O P R O C E S S O R S & S U P P O R T C IR C U IT S 2 2 -2 7 28 2 9 -3 0 DTL TTL L IN E A R IN T E R F A C E C IR C U IT S 5 5 / 7 5 S e rie s C o n tr o l C ir c u its C ro s s -R e fe re n c e G u id e

S8830

Contextual Info: + Na t i o na l Semiconductor & M ay 1998 D a U -~i at O /) ^1 oo ro o aU) O N> DS78C20/DS88C20 Dual CMOS Compatible Differential Line Receiver at at O O (/) ro o oo oo General Description Features The D S78C 20 and D S88C 20 are high perform ance, dual d if­

DS8820A

Contextual Info: M ay 1999 Semiconductor DS7820A/S8820A Dual Line Receiver General Description The response tim e can be controlled w ith an external capaci­ to r to reject input noise spikes. The output state is a logic “ 1” for both inputs open. Term ination resistors fo r the twisted