RST01 Search Results

neural network

Abstract: application of feed back amplifier block diagram of 74LS138 3 to 8 decoder block diagram for neural network connection diagram of ic 74ls138 74LS138 decoder neural network chips
Contextual Info: > NEURAL NETWORK ANALOG CMOS CIRCUITS DENDROST“-1 FEED-FORWARD/FEED-BACK CONNECTION CIRCUIT ARRAY Features: • Performs the equivalent of 4.3 MFLOPS using analog computation • Designed for competitive-type, non-supervised, multi-layer networks • Incorporates sleep-refreshed memory retention mechanism

Contextual Info: MB86933 FUJITSU PRELIMINARY SPARClite 32-BIT RISC EMBEDDED PROCESSOR ADVANCE INFORMATION AUGUST 1992 FEATURES G EN ER A L D E S C R IP T IO N • 20 MHz 50ns/cycle operating frequency The MB86933 is the next of the SPARClite series of RISC processors which offers high performance and

Contextual Info: M B86936 FUJITSU 930 SERIES 32-BIT RISC EMBEDDED PROCESSOR APRIL, 1996 • On-chip clock generator circuit FEATURES • JTAG test interface • 25 and 50 MHz versions • Emulator support hardware • Clock doubler for 50 MHz version • Single vector trapping

kdf4

Contextual Info: DS80CH11 PRELIMINARY DALLAS SEMICONDUCTOR DS80CH11 System Energy Manager PRODUCT SPECIFICATION V1.0 PRELIMINARY 042098 1/88 DS80CH11 TABLE OF CONTENTS 1.0 2.0 3.0 4.0 GENERAL DESCRIPTION .5

RST02

Abstract: LR2000 LR3000
Contextual Info: Chapter 2 LR3201 Reset/Interrupt Controller This chapter describes the LR3201 Reset/Interrupt Controller. This chapter is oiganized into these sections: • General Description ■ Reset Operation ■ Interrupt Operation ■ Signal Definitions ■ Interfacing to the LR3201

LR3000

Abstract: 8196 LR3000 User Manual lr2000 LR3201 mps 0709 LR3000A RST01 mps 1410
Contextual Info: Chapter 2 LR3201 Reset/Interrupt Controller This chapter describes the LR3201 Reset/Interrupt Controller. This chapter is organized into these sections: • General Description ■ Reset Operation ■ Interrupt Operation ■ Signal Definitions ■ Interfacing to the LR3201

ADMX

Contextual Info: DS80CH11 DALLAS SEMICONDUCTOR DS80CH11 System Energy Manager PRODUCT SPECIFICATION V2.0 052499 1/88 r DS80CH11 TABLE OF CONTENTS 1.0 G E N E R A L D E S C R IP T IO N .5

RST01

Abstract: ISP1240 ISP1280 block diagram of risc processor AD630
Contextual Info: QLogic Corporation ISP1280 Intelligent, Dual SCSI Processor Data Sheet Features • ■ ■ ■ ■ ■ ■ ■ ■ No host intervention required to execute SCSI operations from start to finish Simultaneous, multiple logical threads JTAG boundary scan support