RINGING SUBSCRIBER LINE INTERFACE CIRCUIT NXP Search Results

scf 4242

Abstract: ACP331 ACP-331 001H IDT82V1074 IDT82V1671 GKPM
Contextual Info: CHIPSET OF RINGING SUBSCRIBER LINE INTERFACE CIRCUIT RSLIC & QUAD PROGRAMMABLE PCM CODEC IDT82V1671 (RSLIC) IDT82V1074 (CODEC) FEATURES DESCRIPTION • Programmable DC feeding characteristics • Programmable digital filters adapting to different requirements:

scf 4242

Abstract: 82V1671 001H IDT82V1074 IDT82V1671
Contextual Info: CHIPSET OF RINGING SUBSCRIBER LINE INTERFACE CIRCUIT RSLIC & QUAD PROGRAMMABLE PCM CODEC PRELIMINARY IDT82V1671 (RSLIC) IDT82V1074 (CODEC) FEATURES DESCRIPTION • Programmable DC feeding characteristics • Programmable digital filters adapting to different requirements:

scf 4242

Abstract: IDT82V1074 IDT82V1671 ca2315
Contextual Info: CHIPSET OF RINGING SUBSCRIBER LINE INTERFACE CIRCUIT RSLIC & QUAD PROGRAMMABLE PCM CODEC IDT82V1671(RSLIC) IDT82V1671A(RSLIC) IDT82V1074 (CODEC) FEATURES DESCRIPTION • Programmable DC feeding characteristics • Programmable digital filters adapting to different requirements:

IDT82V1671

Abstract: diode T35 12H Ringing Subscriber Line Interface Circuit NXP IDT82V1074 8 output decoder relay driver
Contextual Info: CHIPSET OF RINGING SUBSCRIBER LINE INTERFACE CIRCUIT RSLIC & QUAD PROGRAMMABLE PCM CODEC IDT82V1671(RSLIC) IDT82V1671A(RSLIC) IDT82V1074 (CODEC) FEATURES DESCRIPTION • Programmable DC feeding characteristics • Programmable digital filters adapting to different requirements:

scf 4242

Abstract: 001H IDT82V1074 IDT82V1671 GREG11
Contextual Info: CHIPSET OF RINGING SUBSCRIBER LINE INTERFACE CIRCUIT RSLIC & QUAD PROGRAMMABLE PCM CODEC ADVANCE INFORMATION IDT82V1671 (RSLIC) IDT82V1074 (CODEC) FEATURES DESCRIPTION • Programmable DC feeding characteristics • Programmable digital filters adapting to different requirements:

IDT82V1074

Abstract: IDT82V1671 1N4004 SM-1
Contextual Info: CHIPSET OF RINGING SUBSCRIBER LINE INTERFACE CIRCUIT RSLIC & QUAD PROGRAMMABLE PCM CODEC ADVANCE INFORMATION IDT82V1671 (RSLIC) IDT82V1074 (CODEC) FEATURES DESCRIPTION • Programmable DC feeding characteristics • Programmable digital filters adapting to different requirements:

Contextual Info: CHIPSET OF RINGING SUBSCRIBER LINE INTERFACE CIRCUIT RSLIC & QUAD PROGRAMMABLE PCM CODEC IDT82V1671(RSLIC) IDT82V1671A(RSLIC) IDT82V1074 (CODEC) FEATURES DESCRIPTION • Programmable DC feeding characteristics • Programmable digital filters adapting to different requirements:

2952 controller

Abstract: 2952 PDI Gain Setting Ringing Subscriber Line Interface Circuit NXP 29C48 29C53 PUB43801 29C44
Contextual Info: H ill IwSSmPRIS SEMICONDUCTOR 29C48 FEATURE CONTROL COMB< JUNE 19£ Features • EXTERNAL AND USER PROGRAMMABLE TRANSMIT AND RECEIVE GAIN • PROGRAMMABLE EXTERNAL HYBRID BALANCE NETWORK SELECT • PROGRAMMABLE ANALOG, DIGITAL AND SUBSCRIBER LOOPBACK • PROGRAMMABLE /¿/A-LAW SELECT

tfc 718

Abstract: 29C48 29C53
Contextual Info: hatra 5868455 design MATRA semicond th D E S I G N SEMICOND m J satfiHSS q o o d v s ? m J ~ 94D 00727 D - H U M S llllH llll /VIAim-HARRIS SEMICONDUCTOR 29C48 FEATURE CONTROL COMBO J ANUARY 1987 1ÂTBOIM Features • EXTERNAL AND USER PROGRAMM ABLE TRANSMIT AND RECEIVE GAIN

2914 combo chip in digital communication system

Abstract: 29C53
Contextual Info: inU. iATC 29C48 FEATURE CONTROL COMBO • External and User Programmable Transmit and Receive Gain ■ Programmable /¿/A-Law Select ■ Programmable External Hybrid Balance Network Select ■ Low Power Consumption ■ Secondary Analog Input Channel ■ External Tone Injection to Receive Path

a3300

Abstract: N29C48 TL 8H3 29C48 fxs interface integrated circuit P29C48 HI-3000 29C53AA
Contextual Info: in tei iATC 29C48 FEATURE CONTROL COMBO • E xte rn al an d U s er P ro g ram m a b le ■ P ro g ram m a b le ja /A -L a w S e le c t T ra n s m it an d R e c e iv e G ain a S e c o n d a ry A n alo g In p u t C h an n el ■ P ro g ram m a b le E xte rn al H ybrid B a la n c e

ap 2952

Contextual Info: P R S y ifflO I M O R f in te T ¡a t p 9 Q P « ¡n A FEATURE CONTROL COMBO Flexible Signaling Interface External and User Programmable Transmit and Receive Gain Pin Selectable Channel A or B Operation on the SLD Interface Programmable Internal and External

Contextual Info: intéT iATC 29C51 FEATURE CONTROL COMBO • Programmable /x/A-Law Select ■ External and User Programmable Transmit and Receive Gain ■ Flexible Signaling Interface ■ Programmable Internal and External Hybrid Balance Network Select ■ Secondary Analog Channel

Contextual Info: SEP X 4 1W2 m AT&T Data Sheet August 1993 Microelectronics T7548 Feature-Control Codec with Filters Features Description • External and user-programmable transmit and receive gain The T7548 Feature-Control Codec is a low-cost, user-programmable, fully integrated PCM codec with

T7548

Abstract: LH1263
Contextual Info: = = ' Microelectronics T7548 Feature-Control Codec with Filters Features Description • External and user-programmable transmit and receive gain The T7548 Feature-Control Codec is a low-cost, user-programmable, fully integrated PCM codec with transmit/receive filters. The T7548 device is fabri­

km 1667

Abstract: d 1667
Contextual Info: intJ. 2913 AND 2914 COMBINED SINGLE-CHIP PCM CODEC AND FILTER • 2913 Synchronous Clocks Only, 300 Mil Package ■ Exceptional Analog Performance ■ 28-Pin Plastic Leaded Chip Carrier PLCC for Higher Integration ■ 2914 Asynchronous Clocks, 8th Bit Signaling, Loop Back Test Capability

Contextual Info: intJ. 2916/2917 HMOS COMBINED SINGLE CHIP PCM CODEC AND FILTER 2916 ft-Law, 2.048 MHz Master Clock Fixed Timing Mode for Standard 32-Channel Systems: 2.048 MHz Master Clock 2917 A-Law, 2.048 MHz Master Clock New 16-Pin Package for Higher Linecard Density Low Power HMOS-E Technology

L7583

Abstract: L7583B L8567 T7507 pub 43801
Contextual Info: Data Sheet August 1999 T7507 Quad PCM Codec with Filters, Termination Impedance, and Hybrid Balance Features • 5 V only ■ Low-power, latch-up-free CMOS technology: — 37 mW/channel typical operating power dissipation — 1 mW/channel typical powerdown dissipation

L7583

Abstract: L7583B L8567 T7507
Contextual Info: Data Sheet August 1999 T7507 Quad PCM Codec with Filters, Termination Impedance, and Hybrid Balance Features • 5 V only ■ Low-power, latch-up-free CMOS technology: — 37 mW/channel typical operating power dissipation — 1 mW/channel typical powerdown dissipation

sinusoidal

Abstract: POWER SUPPLY 2916 fxs interface integrated circuit
Contextual Info: in t j, 2916/2917 HMOS COMBINED SINGLE CHIP PCM CODEC AND FILTER 2916 /x-Law, 2.048 MHz Master Clock 2917 A-Law, 2.048 MHz Master Clock New 16-Pin Package for Higher Linecard Density AT&T D3/D4 and CCITT Compatible Variable Timing Mode for Flexible Digital Interface: Supports Data Rates

GSR-V

Abstract: DIP20 M5913 M5913B1
Contextual Info: M5913 COMBINED SINGLE CHIP PCM CODEC AND FILTER SYNCHRONOUS CLOCKS ONLY AT&T D3/D4 AND CCITT COMPATIBLE TWO TIMING MODES: FIXED DATA RATE MODE 1.536MHz, 1.544MHz, 2.048MHz VARIABLE DATA MODE: 64KHz - 4.096MHz PIN SELECTABLE µ-LAW OR A-LAW OPERATION NO EXTERNAL COMPONENTS FOR SAMPLE-AND-HOLD AND AUTO ZERO FUNCTIONS

DIP20

Abstract: M5913 M5913B1
Contextual Info: M5913 COMBINED SINGLE CHIP PCM CODEC AND FILTER SYNCHRONOUS CLOCKS ONLY AT&T D3/D4 AND CCITT COMPATIBLE TWO TIMING MODES: FIXED DATA RATE MODE 1.536MHz, 1.544MHz, 2.048MHz VARIABLE DATA MODE: 64KHz - 4.096MHz PIN SELECTABLE µ-LAW OR A-LAW OPERATION NO EXTERNAL COMPONENTS FOR SAMPLE-AND-HOLD AND AUTO ZERO FUNCTIONS

legerity lucent

Contextual Info: • ■ ■ ■ ■ 5 V only SI D D GN E D E S FO VIC R E ■ Description Low-power, latch-up-free CMOS technology: — 37 mW/channel typical operating power dissipation — 1 mW/channel typical powerdown dissipation Fixed master clock frequency: 2.048 MHz

DIGITA ECHO DELAY

Contextual Info: 2913 AND 2914 COMBINED SINGLE-CHIP PCM CODEC AND FILTER • 2913 Synchronous Clocks Only, 300 Mil Package ■ 2914 Asynchronous Clocks, 8th Bit Signaling, Loop Back Test Capability ■ AT&T D3/D4 and CCITT Compatible for Synchronous Operation ■ Pin Selectable jn-Law or A-Law