REVISED Search Results

54HC573

Contextual Info: SN54HC573, SN74HC573 OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS D26B4. DECEMBER 1982-REVISED SEPTEMBER 1987 • High-Current 3-State Output Drive Bus-Lines Directly or Up to 15 LSTTL Loads • Bus-Structured Pinout Package Options Include Plastic "Small

Contextual Info: TLE2037, TLE2037A EXCALIBUR LOW -NOISE HIGH-SPEED PRECISION DECOM PENSATED OPERATIONAL AM PLIFIERS D3454, MAY 1990 - REVISED APRIL 1991 available features Outstanding Combination of DC Precision and AC Performance: Gain-Bandwldth Product. . . 80 MHz Typ V

A1619A

Abstract: b1241
Contextual Info: SN54ABT32318, SN74ABT32318 18-BIT TRI-PORT UNIVERSAL BUS EXCHANGERS SCBS180A-JUNE 1 9 9 2 - REVISED JULY 1994 Members of the Texas Instruments Wldebus+ Family State-of-the-Art EPIC-IlB™ BICMOS Design Significantly Reduces Power Dissipation Typical V q l p Output Ground Bounce

Contextual Info: SN54ALS259, SN74ALS259 8 BIT AD D R E S S A B LE LA TC HES D2661, DECEMBER 1982-REVISED MAY 1986 S N 5 4 A L S 2 5 9 . J PACKAGE S N 7 4 A L S 2 5 9 . . . D OR N PACKAGE 8-Bit Parallel-Out Storage Register Performs Serial-to-Parallel Conversion with Storage

Contextual Info: 54AC11109, 74AC11109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET TI0066— D2957, M ARCH 1987— REVISED M ARCH 1990 Flow-Through Architecture to Optimize PCB Layout 54AC11109 . . . J PACKAGE 74AC11109 . . . D OR N PACKAGE TOP VIEW

Contextual Info: SN75LBC241 LOW-POWER LinBiCMOS MULTIPLE DRIVERS AND RECEIVERS SLLS137E - MAY 1992 - REVISED JANUARY 1999 • Operates With Single 5-V Power Supply • Meets or Exceeds the Requirements of TIA/EIA-232-F and ITU Recommendation V.28 • Improved Performance Replacement for

SN74HC74

Contextual Info: SN54HC74, SN74HC74 DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET _ SCLS094A - DECEMBER 1982 - REVISED JANUARY 1996 Package Options Include Plastic Small-Outline D , Shrink Small-Outline (DB), Thin Shrink Small-Outline (PW), and

75ALS126

Abstract: mw137 n75a LS126 SN75129
Contextual Info: SN55ALS126, $N75ALS126 QUADRUPLE LINE DRIVERS D2299, FEBRUARY 1 9 8 6 -REVISED OCTOBER 1989 S N 55A LS126. S N 75A LS126 . . . J PACKAGE S N 75A LS126 . . . D OR N PACKAGE Meets IBM 3 6 0 /3 7 0 I/O Interface Specification G A22-6974-3 Also See SN55ALS130 and SN75ALS130

Contextual Info: SN74BCT29854 8-BIT TO 9-BIT PARITY BUS TRANSCEIVER S C B S 257- SEPTEMBER 1987 - REVISED NOVEMBER 1993 DW OR NT PACKAGE • BICMOS Process With TTL Inputs and Outputs T O P V IE W • State-of-the-Art BICMOS Design Significantly Reduces Standby Current

7408, 7404, 7486, 7432

Abstract: RF400U functional diagram of 7400 and cd 4011 ls 7404 180 nm CMOS standard cell library TEXAS INSTRUMENTS 74191 4BITS s273 buffer 74374 7408 CMOS cmos 7404
Contextual Info: TGC100 Series CMOS Gate Arrays RELEASE 3.0, REVISED JANUARY 1990 • Twelve Arrays with up to 26K Available Gates • Fast Prototype Turnaround Time • Extensive Design Support - Design Libraries Compatible with Daisy, Valid, and Mentor CAE Systems - Tl Regional ASIC Design Centers

Contextual Info: 54AC11032, 74AC11032 QUADRUPLE 2-INPUT POSITIVE-OR GATES TI0060— D2957, JULY 1987— REVISED MARCH 1990 54A C 11032 . . . J PACKAGE 74A C 11032 . . . D OR N PACKAGE • Flow-Through Architecture to Optimize PCB Layout TOP VIEW • Center-Pin V c c and GND Configurations to

IR 30 D1

Contextual Info: SN74ALS236 64 x 4 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY SDAS107A-OCTOBER 1986 - REVISED SEPTEMBER 1993 Asynchronous Operation Organized as 64 Words by 4 Bits DW OR N PACKAGE TOP VIEW r NC [ 1 Data Rates From 0 to 30 MHz 3-State Outputs 16 J VCC 15 ] S O

tr8c

Abstract: TMS28F200
Contextual Info: TMS28F20ÛBZT, TMS28F200BZB 262144 BY 8-BIT/131072 BY 16-BIT BOOT-BLOCK FLASH MEMORIES SWS2dOO - JUNE 1 9 9 4 - REVISED SEPTEMBER 1997 • ■ I I I • • • • • • • • • • Organization . . . 262144 by 8 bits 131072 by 16 bits Array-Blocking Architecture

sn 74 ls 11 020 n

Abstract: LS1020A LS102
Contextual Info: SN 54A LS1020A , S N 74 A LS 1 020 A DUAL 4-INPUT POSITIVE-NAND BUFFERS D2661, APRIL 1982-REVISED MAY 1986 • Buffer Version of 'A LS20B • Package Options Include Plastic "Sm all Outline" Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-m il

Contextual Info: SN74F378 HEX D-TYPE FLIP-FLOP WITH CLOCK ENABLE S D FS 030B - D2932, M ARCH 1987 - REVISED O CTO B ER 1993 Contains Six D-Type Flip-Flops With Single-Rail Outputs Applications Include: Buffer/Storage Registers Shift Registers Pattern Generators Buffered Common Enable Input

Contextual Info: 54AC11021,74AC11021 DUAL 4-INPUT POSITIVE-AND GATES _ D2957. JULY 1987 - REVISED APRIL 1993 54AC11021 . . . J PACKAGE 74AC11021 . . . D OR N PACKAGE TOP VIEW * Flow-Through Architecture Optimizes PCB Layout * Center-Pin Vcc and GND Configurations

Contextual Info: 54AC11002, 74AC11002 QUADRUPLE 2-INPUT POSITIVE-NOR GATES D2957, JUNE 1987 - REVISED APRIL 1993 54AC11002 . . . J PACKAGE 74AC11002 . . . D OR N PACKAGE TOP VIEW Flow-Through Architecture Optimizes PCB Layout Center-Pin Vcc and GND Configuration Minimizes High-Speed Switching Noise

Contextual Info: BUCHANAN Catalog 1308389 Terminal Blocks Revised 12-02 TW O-PIECE TERM IN AL B L O C K C O N N EC TO R S 14.4 max. Straight, Closed End Headers, w'Ejectors, 5.08 mm Centerline C o lo r-G re e n .567 12.25 min. A52 H UL R a tin g -3 0 0 V, 15 A 9J5 nhTt Ji

Contextual Info: THIS DRAWING IS UNPUBLISHED. COPYRIGHT RELEASED FOR PUBLICATION BY TYCO ELECTRONICS CORPORATION. - LOC DIST CM 00 ALL RIGHTS RESERVED. REVISIONS LTR DESCRIPTION REVISED PER 0G 3B - 0 2 8 5 - 0 4 DATE DWN APVD 02APR04 KW CJ D D 2 4 .8 9 + 0 .3 8 0 .6 4 [.0 2 5 ]

Contextual Info: THIS DRAWING IS COPYRIGHT UNPUBLISHED. 20 RELEASED BY TYCO ELECTRONICS CORPORATION FOR ALL 20 PUBLICATION RIGHTS LOC RESERVED. REV I S IONS D I ST FT LTR DESCRIPTION REVISED -TEST C L A M P I NG SCREW­ / ^ DWN DATE P E R 0 G 3 B - 0 I 19-01 APVD EZ 3 I OCT 2 0 0 I

ST NE556

Abstract: NES56 NE556J NE556 applications NE555
Contextual Info: NES56, SA556, SE556, SE556C DUAL PRECISION TIMERS SLFS023A - A P R IL 1978 - REVISED O CTO BER 1992 • Two Precision Timing Circuits per Package • Astable or Monostable Operation • TTL-Compatible Output Can Sink or Source Up to 150mA • Active Pullup or Pulldown

Contextual Info: TL16C550C ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH AUTOFLOW CONTROL SLLS177B- MARCH 1994 - REVISED MARCH 1996 • Programmable Auto-RTS and Auto-CTS • In Auto-CTS Mode, CTS Controls Transmitter • In Auto-RTS Mode, RCV FIFO Contents and Threshold Control RTS

TLE2062B

Contextual Info: TLE2062, TLE2062A, TLE2062B, TLE2062Y EXCALIBUR JFET-INPUT HIGH-OUTPUT-DRIVE jiPOW ER DUAL OPERATIONAL AM PLIFIERS D3346, OCTOBER 1989 - REVISED NOVEMBER 1991 availablefeatures • Excellent Output Drive Capability V 0 = ± 2.5 V Min at R|_ = 100 Q , VC C ± = ± 5 V

d3905

Contextual Info: TL7759C SUPPLY VOLTAGE SUPERVISOR D3905. JANUARY 1991-REVISED SEPTEMBER 1991 D OR P PACKAGE TOP VIEW * Power-On Reset Generator * Automatic Reset Generation After Voltage Drop * Precision Threshold Voltage 4.55 V ±120 mV * Low Standby Current, . . 20 ^A