REVA1113 Search Results

Contextual Info: CTS100EL16 LVPECL Oscillator Gain Stage & Buffer with Enable MLP8, MSOP8, MSOP10 Features      Block Diagram 250ps Propagation Delay High Voltage Gain vs. Standard EL16 75k Enable Pull-down Resistor High Bandwidth for 1GHz -147 dBc/Hz Typical Noise Floor

Contextual Info: CTSLV394 LVPECL Divide by 1, Divide by 2 Clock Generator w/ Tri-State Compatible Outputs MLP8 Features          Block Diagram Selectable Divide Ratio Selectable Enable Priority and Threshold CMOS or PECL Tristate Compatible Outputs

SON8

Contextual Info: CTSLV363 Low Phase Noise LVPECL Buffer and Translator SON8 Features Block Diagram LVPECL Outputs Optimized for Very Low Phase Noise -165dBc/Hz  Up to 1GHz Bandwidth  Selectable ÷1, ÷2 Output  Selectable Enable Logic  3.0V to 3.6V Operation

Contextual Info: CTSLV392 LVPECL Divide by 1, Divide by 2 Clock Generator w/ Selectable Enable MLP8 Features        Block Diagram Selectable Divide Ratio Selectable Enable Priority and Threshold CMOS or PECL 3.0V to 5.5V Power Supply -145dBc/Hz (÷1) Typical Noise Floor

Contextual Info: CTS100ELT23 Dual Differential PECL to CMOS/TTL Translator MSOP8, SOIC8 Features Block Diagram   3.5ns Typical Propagation Delay <500ps Typical Output to Output Skew  Differential PECL Inputs  Flow Through Pinouts  CMOS/TTL Outputs  RoHS Compliant Pb Free Packages

QFN8

Contextual Info: CTSLV353 Low Phase Noise LVPECL Buffer and Translator QFN8, SON8 Features Block Diagram LVPECL Outputs Optimized for Very Low Phase Noise -165dBc/Hz  Up to 800MHz Bandwidth  Selectable ÷1, ÷2 Output  Selectable Enable Logic  3.0V to 3.6V Operation

Contextual Info: CTSLVEL16VT PECL/ECL Oscillator Gain Stage & Buffer with Selectable Enable MLP8 Block Diagram Features     Minimizes External Components High Bandwidth for 1GHz Similar Operation as CTSLVEL16VR Except in Disabled Condition QHG is High -147 dBc/Hz Typical Noise Floor

marking+3610

Contextual Info: CTSLVEL16VV Dual Frequency PECL/ECL Oscillator Gain Stage & Buffer with Enable MLP16 Features     Block Diagram Minimizes External Components Similar Operation as CTSLVEL16VR except with Selectable Data Input Pairs High Bandwidth for 1GHz -147 dBc/Hz Typical Noise Floor

Contextual Info: CTS100LVEL58 LVPECL 2:1 Multiplexer MLP8, MSOP8, SOIC8 Features       Block Diagram 440ps Propagation Delay  Operating Voltage of 3.0 to 5.5V Internal Input Pull-down Resistors Direct Replacement for ON Semi MC100LVEL58 ROHS Compliant Pb Free Packages

CTS10

Contextual Info: CTS10EL89 PECL/ECL Coaxial Cable Driver SOIC8 Features  Block Diagram Direct Replacement for ON Semi MC10EL89  1.6V Output Swing  375ps Propagation Delay  Internal Input Pull-down Resistors  RoHS Compliant Pb Free Packages  Description

Contextual Info: CTSLVEL16VR PECL/ECL Oscillator Gain Stage & Buffer with Selectable Enable MLP8, MLP16 Features      Block Diagram Minimizes External Components Selectable Enable Polarity and Threshold CMOS or PECL High Bandwidth for 1GHz Similar Operation as CTS100EL16

Contextual Info: CTST571 Programmable Capacitive Tuning IC SON8, MLP6 Block Diagram Features       Capacitive Tuning Range of 6.6pF to 37.553pF 0.063pF Minimum Step Size Continually Programmable with Register or EEPROM Data Storage May Be Placed in Parallel for Greater

Contextual Info: CTSLV310 Ultra-Low Phase Noise LVPECL, LVDS Buffer and Translator SON8, MSOP8 Features Block Diagram 2.5V-3.3V Operation Ultra-Low Phase Noise Floor • LVPECL -167dBc/Hz  LVDS -165dBc/Hz  Configurable  LVPECL or LVDS Output  ÷1 or ÷2  Enable Active High or Low

Contextual Info: CTSLV351 Low Phase Noise LVPECL Buffer & Translator SC70-6 Features Block Diagram LVPECL Outputs Optimized for Very Low Phase Noise -165dBc/Hz  Up to 800MHz Bandwidth  Selectable ÷1, ÷2 Output  Selectable Enable Logic  3.0V to 3.6V Operation

Contextual Info: CTS100ELT22 Dual CMOS/TTL to Differential PECL Translator MSOP8, SOIC8 Block Diagram Features      0.5ns Typical Propogation Delay <100ps Typical Output to Output Skew Flow Through Pinouts Differential PECL Output RoHS Compliant Pb Free Packages

Contextual Info: CTS100LVEL11 LVPECL 1:2 Differential Fan-out Buffer MLP8, MSOP8, SOIC8 Features Block Diagram 265ps Propagation Delay 5ps Skew Between Outputs Internal Input Pull-Down Resistors Direct Replace for ON Semi MC100LVEL11 and MC100EL11  RoHS Compliant Pb Free Packages

Contextual Info: CTSLV315 Ultra-Low Phase Noise LVPECL, LVDS Buffer and Translator with Gain SON8, MSOP8 Features Block Diagram 2.5V-3.3V Operation Ultra-Low Phase Noise Floor • LVPECL -167dBc/Hz  LVDS -165dBc/Hz  Configurable  LVPECL or LVDS Output  ÷1 or ÷2