REGULATOR 4FB Search Results

IR9494

Abstract: IR9494N
Contextual Info: Switching Regulator Control Circuit IR9494/IR9494N I R 9 4 9 4 /IR 9 4 9 4 N • ■ D escription Control Pin Connections The IR9494/IR9494N is a fixed frequency Pulse Width-Modulation control circuit. It includes most functions required for control circuits.

4FB3

Abstract: J4B3
Contextual Info: SJ431/SJF431 Semiconductor Programmable Voltage Reference ◈ Description The SJ431 series are 3-terminal precision shunt regulators that are programmable over a wide voltage range of 2.495V to 18V with ±0.5%, ±1.0% tolerance. The SJ431 series have a low dynamic impedance of 0.15Ω. These

Contextual Info: SJ431/SJF431 Semiconductor Programmable Voltage Reference ◈ Description The SJ431 series are 3-terminal precision shunt regulators that are programmable over a wide voltage range of 2.495V to 18V with ±0.5%, ±1.0% tolerance. The SJ431 series have a low dynamic impedance of 0.15Ω. These

Contextual Info: SJ431/SJF431 Semiconductor Programmable Voltage Reference ◈ Description The SJ431 series are 3-terminal precision shunt regulators that are programmable over a wide voltage range of 2.495V to 18V with ±0.5%, ±1.0% tolerance. The SJ431 series have a low dynamic impedance of 0.15Ω. These

Contextual Info: Application Note 1070 Design Guideline and Application Notes of AP1681 System Solution Prepared by Wang Zhao Kun System Engineering Dept. 1. Introduction • The AP1681 is a powerful high performance AC/DC power supply controller for dimmable LED lighting applications.

Contextual Info: TOSHIBA TENTATIVE TA1281F/FA/FN TOSHIBA BIPOLAR LINEAR INTEGRATED CIRCUIT T• «Am 1 a ? » 1u uF g Tu mA » 1■ ? R 1m uFm A m g SILICON MONOLITHIC Tu mA m. 1u 7 8 1■ ■ F N u m UHF/VHF TUNER IC The TA1281F, TA1281FA, and TA1281FN are TV tuner ICs which integrate on a single chip IF amp, a mixer/

LG MS 7541 MOTHERBOARD SERVICE MANUAL

Abstract: DDR3 DRAM layout AM2r2 Processor Functional amd socket s1g4 ED58 diode lg monitor 700e diagram A854 TOM - 2088 - BH IC TOP 8901 AMD Infrastructure Roadmap
Contextual Info: 31116 Rev 3.48 - April 22, 2010 AMD Family 10h Processor BKDG Cover page BIOS and Kernel Developer’s Guide BKDG For AMD Family 10h Processors Advanced Micro Devices 1 31116 Rev 3.48 - April 22, 2010 AMD Family 10h Processor BKDG 2005–2010 Advanced Micro Devices, Inc. All rights reserved.

CX86810

Abstract: DFX209-C DFX209 DFX214 102366B 2713Hz cos v21 l10 TR-TSY-000031 DFX2-14 conexant EQM
Contextual Info: CX86810 DFX214/DFX209 14400/9600 bps Fax Modem Design Guide Preliminary Conexant Proprietary Information Conexant Confidential Information Dissemination, disclosure, or use of this information is not permitted without the written permission of Conexant Systems, Inc.

telephone* -"transmission lines" awg attenuation

Abstract: DS5130 MT9171 MT9171AE MT9171AN MT9171AP MT9172 MT9172AE MT9172AN MT9172AP
Contextual Info: ISO2-CMOS ST-BUS FAMILY MT9171/72 Digital Subscriber Interface Circuit Digital Network Interface Circuit Features • • • • • • • • • DS5130 • • February 1999 Ordering Information MT9171AE 22 Pin Plastic DIP 400 mil MT9171AN 24 Pin SSOP

MT8971B

Abstract: MT8971BE MT8971BP MT8972B MT8972BC MT8972BE MT8972BP
Contextual Info:  ISO2-CMOS ST-BUS FAMILY MT8971B/72B Digital Subscriber Interface Circuit Digital Network Interface Circuit Features • • • • • • • • • ISSUE 7 Full duplex transmission over a single twisted pair Selectable 80 or 160 kbit/s line rate

MT9171

Abstract: MT9171AE MT9171AN MT9171AP MT9172 MT9172AC MT9172AE MT9172AN MT9172AP
Contextual Info:  ISO2-CMOS ST-BUS FAMILY MT9171/72 Digital Subscriber Interface Circuit Digital Network Interface Circuit Features • • • • • • • • • ISSUE 1 Full duplex transmission over a single twisted pair Selectable 80 or 160 kbit/s line rate Adaptive echo cancellation

Contextual Info: is o 2-c m o s st-b us fa m ily M ITEL Digital Subscriber Interface Circuit with RxSB Digital Network Interface Circuit with RxSB Features ISSUE 2 R eceive sync output pulse • Full duplex transm ission o ve r a single twisted pair • S electable 80 o r 160 kbit/s line rate

Contextual Info: IS 02-CM0S ST-BUS f a m il y M T 9 1 7 1 /7 2 Digital Subscriber Interface Circuit MITEL Digital Network Interface Circuit IS S U E 1 Features • Full duplex transmission over a single twisted pair Selectable 80 or 160 kbit/s line rate Ordering Information

Contextual Info: M T 9 1 71/72 is o 2- c m o s s t-b u s f a m ily M IT E L Digital Subscriber Interface Circuit Digital Network Interface Circuit Features • ISSUE 2 Full duplex transm ission over a single tw isted pair • Selectable 80 or 160 kbit/s line rate • Adaptive echo cancellation

telephone* -"transmission lines" awg attenuation

Abstract: cdi circuit diagram MT9171AP MT9172 MT9172AE MT9172AN MT9172AP DS5130 MT9171 MT9171AE
Contextual Info: ISO2-CMOS ST-BUS FAMILY MT9171/72 Digital Subscriber Interface Circuit Digital Network Interface Circuit Features • • • • • • • • • DS5130 • • February 1999 Ordering Information MT9171AE 22 Pin Plastic DIP 400 mil MT9171AN 24 Pin SSOP

DS5130

Abstract: cdi circuit diagram MT9172AE MT9172AN MT9172AP MT9171 MT9171AE MT9171AN MT9171AP MT9172
Contextual Info: ISO2-CMOS ST-BUS FAMILY MT9171/72 Digital Subscriber Interface Circuit Digital Network Interface Circuit Features • • • • • • • • • DS5130 • • February 1999 Ordering Information MT9171AE 22 Pin Plastic DIP 400 mil MT9171AN 24 Pin SSOP

Contextual Info: MITEL i s o 2-C m o s s t - b u s f a m il y Digital Subscriber Interface Circuit Digital Network Interface Circuit Features • • • • • • • • • ISSUE 7 Full duplex transmission over a single twisted pair Selectable 80 or 160 kbit/s line rate

R5F100LEA

Abstract: R5F100 R5F100AA R5F100LE R5F100ACDSP R5F100AE R01US0015E R20UT0008E R5F101 R5F10
Contextual Info: User’s Manual 16 RL78/G13 User’s Manual: Hardware 16-Bit Single-Chip Microcontrollers All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by

R5F100LE

Abstract: R01US0015E R5F100LEA R5F10 R5F100GEAFB R5F100GL Murata SFr 450 filter R5F100FE R5F101GDAFB R5F100LEAFA
Contextual Info: User’s Manual 16 RL78/G13 User’s Manual: Hardware 16-Bit Single-Chip Microcontrollers All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by

MT9174AE

Abstract: MT9174AN MT9174AP MT9173 MT9173AE MT9173AN MT9173AP MT9174 TC 9151 P
Contextual Info: ISO2-CMOS ST-BUS FAMILY MT9173/74 Digital Subscriber Interface Circuit with RxSB Digital Network Interface Circuit with RxSB Features • • DS5131 • • • • • • Receive sync output pulse Full duplex transmission over a single twisted pair Selectable 80 or 160 kbit/s line rate

Contextual Info: ISO2-CMOS ST-BUS FAMILY MT9173/74 Digital Subscriber Interface Circuit with RxSB Digital Network Interface Circuit with RxSB Features • • DS5131 • • • • • • Receive sync output pulse Full duplex transmission over a single twisted pair Selectable 80 or 160 kbit/s line rate

Biphase decoder

Abstract: cdi unit zarlink modem DS5130 MT9171 MT9171AE MT9171AN MT9171AP MT9172 MT9172AE
Contextual Info: ISO2-CMOS ST-BUS FAMILY MT9171/72 Digital Subscriber Interface Circuit Digital Network Interface Circuit Features • • • • • • • • • DS5130 • • February 1999 Ordering Information MT9171AE 22 Pin Plastic DIP 400 mil MT9171AN 24 Pin SSOP

TC 9151 P

Abstract: MT9173 MT9173AE MT9173AN MT9173AP MT9174 MT9174AE MT9174AN MT9174AP zpd n
Contextual Info: ISO2-CMOS ST-BUS FAMILY MT9173/74 Digital Subscriber Interface Circuit with RxSB Digital Network Interface Circuit with RxSB Features • • DS5131 • • • • • • Receive sync output pulse Full duplex transmission over a single twisted pair Selectable 80 or 160 kbit/s line rate

Telecom

Abstract: detailed circuit dc cdi timing dc dc for CDI Circuit cdi circuit diagram C333P Philips Varistors detailed circuit dc cdi
Contextual Info: ISO2-CMOS ST-BUS FAMILY MT9171/72 Digital Subscriber Interface Circuit Digital Network Interface Circuit Data Sheet Features March 2006 • Full duplex transmission over a single twisted pair • Selectable 80 or 160 kbit/s line rate • Adaptive echo cancellation