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    ddr3 dram layout Datasheets

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    Part ECAD Model Manufacturer Description Download Buy
    TS3DDR3812RUAR Texas Instruments 12-channel, 1:2 MUX & DEMUX switch for DDR3 applications 42-WQFN -40 to 85 Visit Texas Instruments Buy
    TS3DDR4000ZBAR Texas Instruments 12-Bits 1:2 High Speed DDR2/DDR3/DDR4 Switch/Multiplexer 48-NFBGA -40 to 85 Visit Texas Instruments Buy
    V62/12602-01XE Texas Instruments Enhanced Product DDR1, DDR2, DDR3 Switcher and LDO 20-HTSSOP -55 to 125 Visit Texas Instruments
    TPS51116MPWPREP Texas Instruments Enhanced Product DDR1, DDR2, DDR3 Switcher and LDO 20-HTSSOP -55 to 125 Visit Texas Instruments
    TPS51116MPWPEP Texas Instruments Enhanced Product DDR1, DDR2, DDR3 Switcher and LDO 20-HTSSOP -55 to 125 Visit Texas Instruments Buy
    TPS51216MRUKREP Texas Instruments Enhanced Product Complete DDR2, DDR3 and DDR3L Memory Power Solution Synchronous Buck Controller 20-WQFN -55 to 125 Visit Texas Instruments Buy

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    JESD79-3D

    Abstract: No abstract text available
    Text: command No Yes Low power Auto self-refresh No Yes TM 10 • DDR3 DRAM provides 25% power savings over DDR2 • DDR3L DRAM provides 15% power saving over DDR3 • DDR4 , are deploying and expect DDR3 support on their new product offerings, especially since the price , DDR3 support • Many of the QorIQ devices offer DDR3L support • Freescale devices with DDR3 /DDR3L support provide customers with higher performance memories at lower powerconsumptions


    Original     		PDF

    2008 - DDR3 pcb layout

    Abstract: DDR3 layout DDR3 DIMM 240 pin names DDR3 pcb layout motherboard DDR3 pcb design DDR3 DIMM 240 pin DIMM DDR3 signal assignments DDR3 timing diagram DDR3 DRAM layout DDR3 impedance
    Text: DDR3 designs should also address issues such as analyzing the interface for all possible DRAM and , data will arrive at the correct time to each DDR3 DRAM device on the DIMM. The command/address/control , connects sequentially to each DDR3 DRAM device in a daisy-chain pattern. Figure 1: DDR3 DIMM controller using write leveling The delay from the DDR3 DRAM device on the far left to the device on the far , across the module. The tDQSS (DQS, DQS# rising edge to CK, CK# rising edge) at the DDR3 DRAM device


    Original     		PDF CP-01044-1 DDR3 pcb layout DDR3 layout DDR3 DIMM 240 pin names DDR3 pcb layout motherboard DDR3 pcb design DDR3 DIMM 240 pin DIMM DDR3 signal assignments DDR3 timing diagram DDR3 DRAM layout DDR3 impedance

    2012 - Micron Technology

    Abstract: No abstract text available
    Text: DRAM or just DRAM (DDR, DDR2, DDR3 . etc.) JEDEC standard JESD79E, etc • LPDDRx – Referred to as , %20Note/ DRAM /TN4102.pdf TN-41-04: Dynamic On-Die-Termination TN-41-13: DDR3 Point-to-Point Design Support , Micron DRAM Products Overview August 2013 John Quigley – Micron FAE ©2012 Micron Technology , ecosystem enablement & support Products in PLP ▶ DRAM ▶ NOR ▶ SLC NAND August 27, 2013  , /products/support/plp August 27, 2013 ©2012 Micron Technology, Inc. | 4 DRAM Product Feature


    Original     		PDF 20Note/DRAM/TN4102 TN-41-04: TN-41-13: TN-46-02: TN-46-06: TN-46-11: TN-46-14: TN-47-19: TN-47-20: Micron Technology

    2010 - Not Available

    Abstract: No abstract text available
    Text: and Layout Design Considerations for DDR3 SDRAM Memory Interfaces This document provides general hardware and layout considerations and guidelines for hardware engineers implementing a DDR3 memory , and Layout Design Considerations for DDR3 SDRAM Memory Interfaces, Rev. 5 2 Freescale , critical layer on which clocks are freely routed. Hardware and Layout Design Considerations for DDR3 , Layout Design Considerations for DDR3 SDRAM Memory Interfaces, Rev. 5 Freescale Semiconductor 5


    Original     		PDF AN3940

    2012 - DDR3 sodimm pcb layout

    Abstract: DDR3 pcb layout micron DDR3 pcb layout MT41K512M8
    Text: 4: 204-Pin DDR3 SODIMM, Standard Layout , PCB 1491 (HSZ) PCB 1491, front side populated 2.45 , Module Dimensions Figure 5: 204-Pin DDR3 SODIMM, Reverse Layout , PCB 1492 (HRZ) PCB 1492, back side , -pin, small-outline dual in-line memory module (SODIMM) – Standard (front side) layout , PCB 1491, "HSZ" – Reverse (back side) layout , PCB 1492, "HRZ" • Fast data transfer rates: PC3-12800, PC3-10600 • 4GB , €¢ Backward-compatible with standard 1.5V (±0.075V) DDR3 systems • VDDSPD = 3.0–3.6V • Nominal and dynamic


    Original     		PDF 204-Pin MT8MTF51264HSZ MT8MTF51264HRZ MO-268 204-pin, PC3-12800, PC3-10600 09005aef84fc0fd3 mtf8c512x64hz DDR3 sodimm pcb layout DDR3 pcb layout micron DDR3 pcb layout MT41K512M8

    2012 - Not Available

    Abstract: No abstract text available
    Text: same ball map, they have similar DRAM PCB layout routing. However, the i.MX 6Solo supports only 32-bit DRAM ; therefore, signals D32~D63, DQM4~7, and SDQS4~7 (_B) can be NC. 5.1 DDR3 connections , layout stubs that may affect DDR3 performance. Ideally, the layout should be modified to remove these , layout stubs that may affect DDR3 performance. Ideally, the layout should be modified to remove these , . . . . . . . . . . . .6 DRAM interface requirements for migration . . . . . . . .9 EPD controller


    Original     		PDF AN4397

    2009 - EDE2116ACBG

    Abstract: EDE2116ACBG-1J-F EDE1116AGBG-1J-F DDR3-800D ELPIDA lpddr DDR3-800E EDE1116AGBG EDJ1108DBSE DDR3 layout EDE1032AGBG
    Text: DRAM Selection Guide CONTENTS 1. DDR3 2. DDR3 SDRAM Module 240-pin Registered DIMM , .10 Selection Guide E1454E90 (Ver.9.0) 3 DRAM Selection Guide 1. DDR3 SDRAM Density , Status Remark Ask DDR3 plus function DRAM Selection Guide 2. DDR3 SDRAM Module 240 , SELECTION GUIDE DRAM Selection Guide Document No. E1454E90 (Ver.9.0) Date Published


    Original     		PDF E1454E90 240-pin M01E0706 EDE2116ACBG EDE2116ACBG-1J-F EDE1116AGBG-1J-F DDR3-800D ELPIDA lpddr DDR3-800E EDE1116AGBG EDJ1108DBSE DDR3 layout EDE1032AGBG

    2012 - DDR3 sodimm pcb layout

    Abstract: micron DDR3 pcb layout DDR3 pcb layout micron ddr3 pcb design considerations Micron DDR3 sodimm pcb layout MT8MTF51264HRZ-1G4 DDR3 DRAM layout MT8MTF51264HSZ-1G6
    Text: SODIMM Module Dimensions Module Dimensions Figure 4: 204-Pin DDR3 SODIMM, Standard Layout , PCB 1491 , : 204-Pin DDR3 SODIMM, Reverse Layout , PCB 1492 (HRZ) PCB 1492, back side populated Front view 67.75 , sheet · 204-pin, small-outline dual in-line memory module (SODIMM) ­ Standard (front side) layout , PCB 1491, "HSZ" ­ Reverse (back side) layout , PCB 1492, "HRZ" · Fast data transfer rates: PC3-12800, PC3 , with standard 1.5V (±0.075V) DDR3 systems · VDDSPD = 3.0­3.6V · Nominal and dynamic on-die termination


    Original     		PDF 204-Pin MT8MTF51264HSZ MT8MTF51264HRZ 204-pin, PC3-12800, PC3-10600 09005aef84fc0fd3 mtf8c512x64hz DDR3 sodimm pcb layout micron DDR3 pcb layout DDR3 pcb layout micron ddr3 pcb design considerations Micron DDR3 sodimm pcb layout MT8MTF51264HRZ-1G4 DDR3 DRAM layout MT8MTF51264HSZ-1G6

    2011 - Design Guide for DDR3-1066

    Abstract: DDR3 pcb layout DDR3 pcb layout guide DDR3 layout AN3940 DDR3 pcb layout guidelines DDR3 layout guidelines micron DDR3 pcb layout DDR3 udimm jedec DDR3 sdram pcb layout guidelines
    Text: and Layout Design Considerations for DDR3 SDRAM Memory Interfaces by Networking and Multimedia , current demands. Hardware and Layout Design Considerations for DDR3 SDRAM Memory Interfaces, Rev. 4 2 , pairs on a single critical layer. Hardware and Layout Design Considerations for DDR3 SDRAM Memory , in parallel. Hardware and Layout Design Considerations for DDR3 SDRAM Memory Interfaces, Rev. 4 4 , at each device. Hardware and Layout Design Considerations for DDR3 SDRAM Memory Interfaces, Rev. 4


    Original     		PDF AN3940 Design Guide for DDR3-1066 DDR3 pcb layout DDR3 pcb layout guide DDR3 layout AN3940 DDR3 pcb layout guidelines DDR3 layout guidelines micron DDR3 pcb layout DDR3 udimm jedec DDR3 sdram pcb layout guidelines

    2012 - DDR3 pcb layout

    Abstract: DDR3 sodimm pcb layout MT41K512M8 micron DDR3 pcb layout DDR3 SDRAM micron DDR3 DRAM layout
    Text: SODIMM Module Dimensions Module Dimensions Figure 4: 204-Pin DDR3 SODIMM, Standard Layout , PCB 1491 , : 204-Pin DDR3 SODIMM, Reverse Layout , PCB 1492 (HRZ) PCB 1492, back side populated Front view 67.75 , sheet · 204-pin, small-outline dual in-line memory module (SODIMM) ­ Standard (front side) layout , PCB 1491, "HSZ" ­ Reverse (back side) layout , PCB 1492, "HRZ" · Fast data transfer rates: PC3-12800, PC3 , with standard 1.5V (±0.075V) DDR3 systems · VDDSPD = 3.0­3.6V · Nominal and dynamic on-die termination


    Original     		PDF 204-Pin MT8MTF51264HSZ MT8MTF51264HRZ 204-pin, PC3-12800, PC3-10600 09005aef84fc0fd3 mtf8c512x64hz DDR3 pcb layout DDR3 sodimm pcb layout MT41K512M8 micron DDR3 pcb layout DDR3 SDRAM micron DDR3 DRAM layout

    2009 - DDR3 layout

    Abstract: E0437E E0234E DDR3 timing diagram E0123N Elpida DDR3 users manual DDR3 DRAM layout ELPIDA DDR3 ELPIDA DDR manual DDR3 impedance
    Text: using double data rate 3 synchronous DRAM ( DDR3 SDRAM). Readers of this manual are required to have , DRAM can be suppressed by controlling ON/OFF of the ODT pin (input: high/low). DDR3 SDRAM can , , DDR2, AND DDR3 ) [Description] The DRAM feeds back the current status on the DQ pin (0: early, 1 , USER'S MANUAL New Features of DDR3 SDRAM Document No. E1503E10 (Ver.1.0) Date Published , of the functions and usage of conventional synchronous DRAM (SDRAM), double data rate synchronous


    Original     		PDF E1503E10 M01E0706 DDR3 layout E0437E E0234E DDR3 timing diagram E0123N Elpida DDR3 users manual DDR3 DRAM layout ELPIDA DDR3 ELPIDA DDR manual DDR3 impedance

    2010 - DDR3 pcb layout guidelines

    Abstract: DDR3 pcb layout guide AN3940 Design Guide for DDR3-1066 DDR3 pcb layout DDR3 layout DDR3 sdram pcb layout guidelines micron ddr3 hardware design consideration DDR3 x16 rank pcb layout DDR3 pcb layout motherboard
    Text: and Layout Design Considerations for DDR3 SDRAM Memory Interfaces by Networking and Multimedia , Layout Design Considerations for DDR3 SDRAM Memory Interfaces, Rev. 3 2 Freescale Semiconductor , signals = 4x. Hardware and Layout Design Considerations for DDR3 SDRAM Memory Interfaces, Rev. 3 , controller pin to the DDR3 DRAM chip pin. After obtaining the MCK to DQS for each byte lane, do the , individual data bits across different byte lanes. Hardware and Layout Design Considerations for DDR3 SDRAM


    Original     		PDF AN3940 DDR3 pcb layout guidelines DDR3 pcb layout guide AN3940 Design Guide for DDR3-1066 DDR3 pcb layout DDR3 layout DDR3 sdram pcb layout guidelines micron ddr3 hardware design consideration DDR3 x16 rank pcb layout DDR3 pcb layout motherboard

    2010 - EDE2116ACBG

    Abstract: EDJ2116DASE ECM220ACBCN ELPIDA EDJ2116DASE EDE1116AGBG EDE2116ACBG-1J-F GDDR5 EDJ1108DBSE-GN-F ELPIDA lpddr EDE1116AGBG-1J-F
    Text: .8 Selection Guide E1610E30 (Ver.3.0) 3 DRAM Selection Guide 1. DDR3 SDRAM Density , SELECTION GUIDE DRAM Selection Guide Document No. E1610E30 (Ver.3.0) Date Published March 2010 (K) Japan Printed in Japan URL: http://www.elpida.com © Elpida Memory, Inc. 2010 DRAM Selection Guide CONTENTS 1. DDR3 2. DDR3 SDRAM Module 240-pin 240-pin Registered DIMM


    Original     		PDF E1610E30 240-pin M01E0706 EDE2116ACBG EDJ2116DASE ECM220ACBCN ELPIDA EDJ2116DASE EDE1116AGBG EDE2116ACBG-1J-F GDDR5 EDJ1108DBSE-GN-F ELPIDA lpddr EDE1116AGBG-1J-F

    2000 - powerchip DDR3

    Abstract: powerchip sdram POWERCHIP DDR3 DRAM layout powertech ELPIDA mobile DDR kingston ddr3 memory Tera Probe Banner Engineering kingston DDR2 800
    Text: fundamental technology research, DRAM circuit/ layout design and its evaluation and analysis, and other , Corporate Profile Be the World's No.1 Our Goal is to Become the World's No. 1 DRAM Solutions , (Elpida) began in December 1999 as Japan's only specialized DRAM maker, the Company has pioneered the use , create extremely productive manufacturing processes. Our goal is to become the No.1 DRAM solutions , semiconductor makers. "Elpida" also represents the idea that we are a Japanese DRAM maker that intends to


    Original     		PDF E0001EC0 powerchip DDR3 powerchip sdram POWERCHIP DDR3 DRAM layout powertech ELPIDA mobile DDR kingston ddr3 memory Tera Probe Banner Engineering kingston DDR2 800

    2010 - DDR3 UDIMM schematic

    Abstract: micron ddr3 hardware design consideration ddr2 ram DDR3 pcb layout guide ddr3 ram UniPHY ddr3 sdram DDR3 pcb layout DDR3 udimm jedec micron ddr3 128 MB DDR2 SDRAM
    Text: , Pin, and Board Layout Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , . . . . . . . . . . . . . . . 2­3 Determine Board Layout . . . . . . . . . . . . . . . . . . . . . , , DDR2, and DDR3 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , Handbook Volume 1: Introduction and Specifications Preliminary iv Chapter 2. DDR, DDR2, and DDR3 , . . . . . . . . 2­1 DDR3 SDRAM Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .


    Original     		PDF

    SAMSUNG 4gb NAND Flash Qualification Report

    Abstract: ddr3 MTBF SAMSUNG 256Mb NAND Flash Qualification Reliability part number decoder toshiba NAND Flash MLC DDR3 pcb layout raw card f so-dimm nand flash socket lga 60 DDR3 sodimm pcb layout samsung microsd card 2gb micron DDR3 pcb layout Hynix 32Gb Nand flash
    Text: INDUSTRIAL MEMORY SOLUTIONS NAND FLASH PRODUCTS & DRAM MODULES Why choose Swissbit Swissbit is the largest independent DRAM module and Flash storage manufacturer in Europe. This enables , service: Product Depth Customization Compliance to -Complete line of DRAM modules and NAND Flash Solid , Engineering Support -Custom DRAM module and Flash designs -Security features -Individual Labeling -Design , -Worlds only COB DRAM memory module manufacturer 2 -Advantest, King Tiger Technology and Tanisys


    Original     		PDF CH-9552 D-12681 SAMSUNG 4gb NAND Flash Qualification Report ddr3 MTBF SAMSUNG 256Mb NAND Flash Qualification Reliability part number decoder toshiba NAND Flash MLC DDR3 pcb layout raw card f so-dimm nand flash socket lga 60 DDR3 sodimm pcb layout samsung microsd card 2gb micron DDR3 pcb layout Hynix 32Gb Nand flash

    Not Available

    Abstract: No abstract text available
    Text: ® GL40 Chipset) Provides up to 8 GByte dual channel DDR3 DRAM DRAM 2 Sockets, SO-DIMM DDR3 1067 , Formfactor COM Express™ Basic, (95 x 125 mm), Type II Connector Layout CPU Intel® Core™ 2 Duo , 047854 COM E 064714 COM E CKIT BM DDR3-SODIMM-1333 (1GB) 068751 DDR3 SODIMM memory module with 1333 MT/s (PC3-10600) and 1GB RAM DDR3-SODIMM-1333 (2GB) 068761 DDR3 SODIMM memory module with 1333 MT/s (PC3-10600) and 2GB RAM 068764 DDR3 SODIMM memory module with 1333 MT


    Original     		PDF conga-BM45 T9400, mPGA479M P8400, T3100 800MHz GM45/GL40 DDR3-SODIMM-1333 1066MHz)

    2004 - J1503E10

    Abstract: J0234E J0123N "DDR3 SDRAM" DDR3 SDRAM DDR3 DDR3 SDRAM Document DDR3 impedance J0123 ELPIDA DDR User
    Text: , ZQCS DRAM 2. OCDOff Chip Driver Calibration: PVT Ron DDR2 OCD 3. DRAM DDR3 DDR3 , (DDR,DDR2 ) 1.1.3 tCCD DDR3 SDRAM 8 DDR2 4 DRAM I/O 8 DRAM I/O 8 READ DRAM READ 8 I/O WRITE I/O DRAM 8 DDR3 8 I/O 1066Mbps 133MHz 133MHz 533MHz , DDR2/ DDR3 SDRAMDRAM DRAM ODT pinInput : High / LowON, OFF DDR3 SDRAMWrite ODTRTT_Nom)Dynamic , . 1-4. ZQ Calibration ZQ Calibration DDR3 DRAM ZQpin =240±1% ZQpin Ron/Rtt 1-5. RZQ ZQ


    Original     		PDF J1503E10 J1503E10 J0123N J0234E J0437E CMJ0107 M01J0706 J0234E J0123N "DDR3 SDRAM" DDR3 SDRAM DDR3 DDR3 SDRAM Document DDR3 impedance J0123 ELPIDA DDR User

    2013 - Armada 375

    Abstract: No abstract text available
    Text: , low-latency, tightly coupled DDR3 /3L DRAM memory controller with advanced transaction re-ordering and , DDR3 /DDR3L 16/32-bit DRAM Controller L1 Icache Integrated BootROM Coherency Fabric , GbE PHY with EEE Integrated GbE PHY with EEE 16/32b DRAM Dual ARMv7 CPU Up to 1GHz 32 KB L1 Dcache 32 KB L1 Icache DDR3 /3L DRAM Flash Interface PCIe 2.0 256-KB L2 Cache PCIe 2.0 , chipsets come with complete reference designs which include board layout designs, software, manufacturing


    Original     		PDF

    2013 - Not Available

    Abstract: No abstract text available
    Text: DDR3 /L DRAM key features and all of the control and address inputs are synchronized with a pair of , random-access memory internally configured as an eight-bank DRAM . The DDR3 /L SDRAM uses a 8n prefetch , the DDR3 /L SDRAM consists of a single 8n-bit wide, four clock data transfer at the internal DRAM core , . Programming bit A7 to a ‘1’ places the DDR3 /L SDRAM into a test mode that is only used by the DRAM , for x8 DRAM and must be disabled for x16. REV 1.1 02/2013 24 1Gb DDR3 F-die SDRAM


    Original     		PDF NT5CB128M8FN NT5CB64M16FP NT5CC128M8FN NT5CC64M16FP x8/x16

    2013 - Not Available

    Abstract: No abstract text available
    Text: High-bandwidth, low-latency coherency fabric High-speed, low-latency, tightly coupled DDR3 /3L DRAM memory , DDR3 /DDR3L 16/32-bit DRAM Controller L1 Icache Integrated BootROM Coherency Fabric , GbE PHY with EEE Integrated GbE PHY with EEE 16/32b DRAM Dual ARMv7 CPU Up to 1GHz 32 KB L1 Dcache 32 KB L1 Icache DDR3 /3L DRAM Flash Interface PCIe 2.0 256-KB L2 Cache , ADVANTAGE: Marvell chipsets come with complete reference designs which include board layout designs


    Original     		PDF

    2013 - Not Available

    Abstract: No abstract text available
    Text: BENEFITS • Large capacity DRAM • 4GB or 8GB DDR3 ECC SODIMMs – Up to 3.2GB/s throughput â , ): 12-16 microseconds NVRAM Capacity • 4GB to 8GB DDR3 DRAM (with ECC protection) with , Marvell DragonFly NVRAM Second-Generation, High-Performance Non-Volatile DRAM Write Cache , ) DDR3 SODIMM and NAND Flash memory to create a large capacity, highly resilient NVRAM technology in a , leverages zeromaintenance ultracapacitors to automatically back up DRAM to SLC NAND Flash in the event of


    Original     		PDF NVRAM-02

    2008 - W2635A-010

    Abstract: ddr3 PCB footprint DDR3 jedec JESD79-3C N5426A DDR3 DIMM footprint N5425A JESD79-3C W2636A-010 DDR3 timing diagram N5451A
    Text: W2635A and W2636A DDR3 BGA probe adapters are soldered in between the DRAM and PC board or DIMM raw , probing for DDR3 compliance test and debug Features · Provides signal access points for DDR3 DRAM x4 , be soldered. Then you can solder the DDR3 DRAM to the top side of the BGA probe adapter. These , of the W2636A DDR3 BGA probe adapter. The top side shows the footprint for DDR3 DRAM and the bottom , . Model number Description W2635A-010 x8, 10 mm width DDR3 BGA probe adapter for x4 and x8 DRAM


    Original     		PDF W2635A W2636A W2635A JESD79-3C) 5989-7643EN W2635A-010 ddr3 PCB footprint DDR3 jedec JESD79-3C N5426A DDR3 DIMM footprint N5425A JESD79-3C W2636A-010 DDR3 timing diagram N5451A

    2012 - NT5CB64M16FP-DH

    Abstract: NT5CB64M16FP nt5cb64m16 NT5CB128M8FN-DH NT5CC64M16FP NT5CB128M8FN NT5CB64M1
    Text: with all key DDR3 /L DRAM key features and all of the control and address inputs are synchronized with a , a high-speed dynamic random-access memory internally configured as an eight-bank DRAM . The DDR3 /L , a `1' places the DDR3 /L SDRAM into a test mode that is only used by the DRAM manufacturer and should , the availability of the first bit of input data. DDR3 /L DRAM does not support any half clock latencies , /L SDRAM: Users should refer to the DRAM supplier data sheet and/or the DIMM SPD to determine if DDR3


    Original     		PDF NT5CB128M8FN/NT5CB64M16FP NT5CC128M8FN/NT5CC64M16FP DDR3/L-1600 DDR3-1866 DDR3-2133 NT5CB64M16FP-DH NT5CB64M16FP nt5cb64m16 NT5CB128M8FN-DH NT5CC64M16FP NT5CB128M8FN NT5CB64M1

    2010 - E2677A

    Abstract: No abstract text available
    Text: W2635A and W2636A DDR3 BGA probe adapters are soldered in between the DRAM and PC board or DIMM raw , probing for DDR3 compliance test and debug Features • Provides signal access points for DDR3 DRAM , DRAM normally would be soldered. Then you can solder the DDR3 DRAM to the top side of the BGA probe , for DDR3 DRAM and the bottom side shows the footprint for a PC board or DIMM card. 2 Superior , width DDR3 BGA probe adapter for x4 and x8 DRAM package W2635A-011 x8, 11 mm width DDR3 BGA probe


    Original     		PDF W2635A W2636A W2635A JESD79-3C) 5989-7643EN E2677A
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