REGISTER WITH TRUTH TABLE Search Results

224 J

Abstract: 54HC 54LS 74HC 74LS C1995 MM54HC195 MM54HC195J MM74HC195 MM74HC195J
Contextual Info: MM54HC195 MM74HC195 4-Bit Parallel Shift Register General Description trol input is high Serial data for this mode is entered at the J-K inputs These inputs allow the first stage to perform as a J-K or TOGGLE flip flop as shown in the truth table The 54HC 74HC logic family is functionally as well as pinout compatible with the standard 54LS 74LS logic family

pn sequence generator using d flip flop

Abstract: pn sequence generator using jk flip flop FULL SUBTRACTOR using 41 MUX full subtractor circuit using xor and nand gates verilog code for 16 bit carry select adder verilog code pipeline ripple carry adder verilog code for jk flip flop vhdl for 8 bit lut multiplier ripple carry adder synchronous updown counter using jk flip flop Mux 1x8 74
Contextual Info: 0373f.fm Page 1 Tuesday, May 25, 1999 8:59 AM Table of Contents Component Generators Introduction .3 AT40K Co-processor FPGAs .4

E0600

Abstract: MACH210 P16H8 binary to bcd decoder 4 digit COUNTER LED bcd 7449 BCD to 7-segment 7449 decoder and seven segment display 7449 7-segment decoder logic diagram IF-6-24 EP600
Contextual Info: ABEL-HDL Reference Table of Contents 1. Introduction 2. Language Structure Summary . . . . . . . . . . . . . . . . . . . . Introduction to ABEL-HDL . . . . . . . . . . Basic Syntax . . . . . . . . . . . . . . . . . . Supported ASCII Characters . . . . . . .

binary to bcd decoder

Abstract: LT 543 7-segment display PAL Decoder 16L8 MACH210 P16R4 P22V10 EP600 P16V8S 7 SEGMENT DISPLAY LT 543 PIN CONFIGURATION diagram ABEL-HDL Reference Manual
Contextual Info: ABEL-HDL Reference Table of Contents 1. Introduction 2. Language Structure Summary . . . . . . . . . . . . . . . . . . . . Introduction to ABEL-HDL . . . . . . . . . . Basic Syntax . . . . . . . . . . . . . . . . . . Supported ASCII Characters . . . . . . .

W942508BH-6

Abstract: W942508BH W942516AH W942516BH
Contextual Info: W942508BH-6 8M x 4 BANKS × 8 BIT DDR SDRAM Table of Contents1. GENERAL DESCRIPTION .3 2. FEATURES .3

W942508BH

Abstract: W942516AH W942516BH
Contextual Info: W942504BH 16M x 4 BANKS × 4 BIT DDR SDRAM Table of Contents1. GENERAL DESCRIPTION .3 2. FEATURES .3

W942508AH

Abstract: W942516AH
Contextual Info: Preliminary W942516AH 4M x 4 BANKS × 16 BIT DDR SDRAM Table of Contents1. GENERAL DESCRIPTION .3 2. FEATURES .3

W942504AH

Abstract: W942508AH W942516AH
Contextual Info: Preliminary W942504AH 16M x 4 BANKS × 4 BIT DDR SDRAM Table of Contents1. GENERAL DESCRIPTION .3 2. FEATURES .3

W942508BH

Abstract: W942516BH W942516BH-6
Contextual Info: W942516BH-6 4M x 4 BANKS × 16 BIT DDR SDRAM Table of Contents1. GENERAL DESCRIPTION .3 2. FEATURES .3

Contextual Info: W9464G6IH 1M x 4 BANKS × 16 BITS DDR SDRAM Table of Contents1. GENERAL DESCRIPTION . 4 2. FEATURES . 4

TA 8270 H

Abstract: TA 8269 H TA 8270 pin configuration BFW 11 8271
Contextual Info: 8269-A,F,W TRUTH TABLE DESCRIPTION The 8269 4-Bit Comparator is an array of gates designed to perform the numerical comparison of two fo u r-b it binary numbers. The outputs indicate whether the tw o num­ bers are equal in value, or which number is the greater. The 8269 is a functional and pinfor-pin replacement for the DM8200.

W9412G6CH

Abstract: a06 transistor DDR266 DDR333 DDR400 DDR444
Contextual Info: W9412G6CH 2M x 4 BANKS × 16 BITS DDR SDRAM Table of Contents1. GENERAL DESCRIPTION . 4 2. FEATURES . 4

Contextual Info: W9425G6JH 4 M  4 BANKS  16 BITS DDR SDRAM Table of Contents1. GENERAL DESCRIPTION. 4 2. FEATURES . 4

W9425G6JH

Contextual Info: W9425G6JH 4 M  4 BANKS  16 BITS DDR SDRAM Table of Contents1. GENERAL DESCRIPTION . 4 2. FEATURES . 4

marking code e14 SMD

Contextual Info: 256Mb: x16, x32 Mobile SDRAM Features Mobile SDRAM MT48H16M16LF – 4 Meg x 16 x 4 banks MT48H8M32LF – 2 Meg x 32 x 4 banks Features Table 1: • Fully synchronous; all signals registered on positive edge of system clock • VDD/VDDQ = 1.70–1.95V • Internal, pipelined operation; column address can

smd transistor marking A10

Abstract: truth table for 8 to 3 decoder AH MARKING SMD MARKING CODE A12 smd marking g8 MT48 MT48H16M16LF MT48H8M32LF BA1A11
Contextual Info: 256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM Features Mobile SDRAM MT48H16M16LF – 4 Meg x 16 x 4 banks MT48H8M32LF – 2 Meg x 32 x 4 banks Features Table 1: • Fully synchronous; all signals registered on positive edge of system clock • VDD/VDDQ = 1.70–1.95V

Contextual Info: Advance‡ 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM Features Mobile SDRAM MT48H32M16LF– 8 Meg x 16 x 4 banks MT48H16M32LF – 4 Meg x 32 x 4 banks For the latest data sheet, refer to Micron’s Web site: http://www.micron.com/mobile Table 1: Features

Contextual Info: 256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM Features Mobile SDRAM MT48H16M16LF – 4 Meg x 16 x 4 banks MT48H8M32LF – 2 Meg x 32 x 4 banks For the latest data sheet, refer to Micron’s Web site: www.micron.com/mobile Features Table 1: • Fully synchronous; all signals registered on positive

D207

Contextual Info: 256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM Features Mobile SDRAM MT48H16M16LF – 4 Meg x 16 x 4 banks MT48H8M32LF – 2 Meg x 32 x 4 banks Features Table 1: • Fully synchronous; all signals registered on positive edge of system clock • VDD/VDDQ = 1.70–1.95V

Contextual Info: W94AD6KB / W94AD2KB 1Gb Mobile LPDDR Table of Contents1. 2. 3. 4. 5. 6. 7. 8. GENERAL DESCRIPTION . 4 FEATURES . 4

Contextual Info: 256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM Features Mobile SDRAM MT48H16M16LF – 4 Meg x 16 x 4 banks MT48H8M32LF – 2 Meg x 32 x 4 banks For the latest data sheet, refer to Micron’s Web site: http://www.micron.com/mobile Features Table 1: • Fully synchronous; all signals registered on positive

Contextual Info: Preliminary‡ 256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM Features Mobile SDRAM MT48H16M16LF – 4 Meg x 16 x 4 banks MT48H8M32LF – 2 Meg x 32 x 4 banks For the latest data sheet, refer to Micron’s Web site: http://www.micron.com/mobile Features Table 1:

urst 1081

Abstract: DDR200 DDR266A DDR266B DDR333 DDR400
Contextual Info: DDR SDRAM Device Operation List of Contents 1. Truth Table 2. State Diagram 3. Device Operation • • • • • • • • • • • • • • • • • • • • • • Power-Up Sequence Burst Read and Burst Write Burst Read followed by Burst Read

Contextual Info: 2533-V DESCRIPTION The 2533 Static Shift Register consists of enhancement mode P-channel silicon gate MOS devices integrated on a single mono­ lithic chip. TRUTH TABLE PIN CONFIGURATION STREAM SELECT F U N C T IO N 1 IN 1 SELECTED IN 2 SELECTED V PACKAGE