REGISTER FILE CONFLICT Search Results

ram 128x16

Abstract: ADSP-3128A ADSP-3128 ADSP3128AKG ABWE microcoded support components
Contextual Info: □ ANALOG DEVICES Multiport Register File ADSP-3128A FEATURES 128x16 or 64x32 Register File Organization Flexible "Crossbar" Data Routing via Five Ports Two Input Two Output One Bidirectional Cascadable Horizontally and Vertically Supports 20MHz Operation from Single 1x Clock

OF IC 741s

Contextual Info: 74S172 Signetics Register File 16-Bit Multiple Port Register File 3-State Product Specification Logic Products FEATURES • Simultaneous and Independent Read and Write operations • Expandable to 1024 words on n-bits • 3-State outputs TYPE TYPICAL SUPPLY CURRENT

H/74S172

Contextual Info: 74S172 Signetics Register File 16-Bit Multiple Port Register File 3-State Product Specification Logic Products FEATURES • Simultaneous and independent Read and Write operations • Expandable to 1024 words on n-bits • 3-State outputs TYPE 74S172 40MHz

1N3064

Abstract: 1N916 74LS 74S172 N74S172N 3HAC
Contextual Info: 74S172 Signefics Register File 16-Bit Multiple Port Register File 3-State Product Specification Logic Products FEATURES • Simultaneous and independent Read and Write operations • Expandable to 1024 words on n-bits • 3-State outputs TYPE Port "A" is an input port which can be

Contextual Info: 74S172 Signetics Register File 16-Bit Multiple Port Register File 3-State Product Specification Logic Products FEATURES • Simultaneous and independent Read and Write operations • Expandable to 1024 words on n-bits • 3-State outputs TYPE Port "A" is an input port which can be

3128A

Abstract: ADSP-3128 DSP32XX ADSP-1401 ADSP-3128A ADSP-32XX ADSP3128AKG microcoded support components UP35 HERO
Contextual Info: ANALO G □ DEVICES Multiport Register File ADSP-3128A FEATURES 128x16 or 6 4 x 3 2 Register File Organization Flexible “Crossbar" Data Routing via Five Ports Tw o Input Tw o Output One Bidirectional Cascadable Horizontally and Vertically Supports 20M H z Operation from Single 1 x Clock

Contextual Info: 74S172 Signetics Register File 16-Bit Multiple Port Register File 3-State Product Specification Logic Products FEATURES • Simultaneous and independent Read and Write operations • Expandable to 1024 words on n-bits • 3-State outputs T h e '1 7 2 is a h ig h -p e rfo rm a n c e , 16-bit

A24D16

Abstract: a32u A241D VAM03 omac vd 100 VAM-03 a64b
Contextual Info: AUGUST 1991 TM CA91C064 VMEbus 64-B IT DATA ADDRESS REGISTER FILE DARF64 64-bit Data/Address Register File (DARF64) T h e C A 9 1 C 0 6 4 D A R F 6 4 provides a complete high per­ form ance VM Ebus 6 4 d a ta transfer interface, including Pin com patible with CA91C015 DARF32

Contextual Info: SN74ALS870 DUAL 16-BY-4 REGISTER FILES SDAS139A - DECEMBER 1982 - REVISED JANUARY 1995 I I I I ' • 3-State Buffer-Type Outputs Drive Bus Lines Directly * Each Register File Has Individual Write-Enable Controls and Address Lines * Designed Specifically for Multibus

ADSP-3128

Abstract: microcoded support components ADSP32xx
Contextual Info: □ ANALOG DEVICES Multiport Register File ADSP-3128A FEATURES 128x16 or 64 x 32 Register Fila Organization Flexible "CroMbar" Data Routing via Five Porta Two Input Two Output One Bidirectional Caacadable Horizontally and Vertically Supporta 20MHz Operation from Single 1 x Clock

ST90R52

Abstract: ST90R52GQ1 PQFP80 st90r50 ST90R
Contextual Info: ST90R52  ROMLESS HCMOS MCU WITH BANKSWITCH AND A/D CONVERTER Register oriented 8/16 bit CORE with RUN, WFI and HALT modes Minimum instruction cycle time: 375ns 16MHz internal 224 general purpose registers available as RAM, accumulators or index pointers (register file)

ST90R50C6

Abstract: ST90R50 ST90R50C ST90R51 ST90R50Q1 PLCC84 PQFP80 B7464 10 35L a5 capacitor ST90R50/R51
Contextual Info: ST90R50  ROMLESS HCMOS MCU WITH BANKSWITCH AND A/D CONVERTER PRELIMINARY DATA Register oriented 8/16 bit CORE with RUN, WFI and HALT modes Minimum instruction cycle time : 500ns 12MHz internal 224 generalpurpose registers available as RAM, accumulators or index pointers (register file)

MS303

Contextual Info: SN74ALS870 DUAL 16-BY-4 REGISTER FILES SOAS139A-DECEMBSR 1982-R E V IS E D JANUARY 1995 • 3-State Buffer-type Outputs Drive Bus Lines Directly • Each Register File Has Individual Write-Enable Controls and Address Lines • Designed Specifically for Multibus

RTL 2832

Abstract: AVR32A marking WMG AVR32UC IEEE-ISTO 5001TM AVR32 AVR32AP AVR32B BOZ 382 BIT1612
Contextual Info: Feature Summary • • • • • • • • • • • Small area, high clock frequency. 32-bit load/store AVR32A RISC architecture. 15 general-purpose 32-bit registers. 32-bit Stack Pointer, Program Counter and Link Register reside in register file.

Contextual Info: SN74ALS870 DUAL 16-BY-4 REGISTER FILES SDAS139A – DECEMBER 1982 – REVISED JANUARY 1995 • • • • • DW OR NT PACKAGE TOP VIEW 3-State Buffer-Type Outputs Drive Bus Lines Directly Each Register File Has Individual Write-Enable Controls and Address Lines

EN12

Abstract: EN13 SN74ALS870 SN74ALS870DW
Contextual Info: SN74ALS870 DUAL 16-BY-4 REGISTER FILES SDAS139A – DECEMBER 1982 – REVISED JANUARY 1995 • • • • • DW OR NT PACKAGE TOP VIEW 3-State Buffer-Type Outputs Drive Bus Lines Directly Each Register File Has Individual Write-Enable Controls and Address Lines

Contextual Info: SN74ALS870 DUAL 16-BY-4 REGISTER FILES SDAS139A – DECEMBER 1982 – REVISED JANUARY 1995 • • • • • DW OR NT PACKAGE TOP VIEW 3-State Buffer-Type Outputs Drive Bus Lines Directly Each Register File Has Individual Write-Enable Controls and Address Lines

51A31

Abstract: EN12 EN13 SN74ALS870
Contextual Info: SN74ALS870 DUAL 16-BY-4 REGISTER FILES SDAS139A – DECEMBER 1982 – REVISED JANUARY 1995 • • • • • DW OR NT PACKAGE TOP VIEW 3-State Buffer-Type Outputs Drive Bus Lines Directly Each Register File Has Individual Write-Enable Controls and Address Lines

Contextual Info: SN74ALS870 DUAL 16-BY-4 REGISTER FILES SDAS139A – DECEMBER 1982 – REVISED JANUARY 1995 • • • • • DW OR NT PACKAGE TOP VIEW 3-State Buffer-Type Outputs Drive Bus Lines Directly Each Register File Has Individual Write-Enable Controls and Address Lines

Contextual Info: SN74ALS870 DUAL 16-BY-4 REGISTER FILES SDAS139A – DECEMBER 1982 – REVISED JANUARY 1995 • • • • • DW OR NT PACKAGE TOP VIEW 3-State Buffer-Type Outputs Drive Bus Lines Directly Each Register File Has Individual Write-Enable Controls and Address Lines

Contextual Info: SN74ALS870 DUAL 16-BY-4 REGISTER FILES SDAS139A – DECEMBER 1982 – REVISED JANUARY 1995 • • • • • DW OR NT PACKAGE TOP VIEW 3-State Buffer-Type Outputs Drive Bus Lines Directly Each Register File Has Individual Write-Enable Controls and Address Lines

EN12

Abstract: EN13 SN74ALS870 multibus ARCHITECTURE
Contextual Info: SN74ALS870 DUAL 16-BY-4 REGISTER FILES SDAS139A – DECEMBER 1982 – REVISED JANUARY 1995 • • • • • DW OR NT PACKAGE TOP VIEW 3-State Buffer-Type Outputs Drive Bus Lines Directly Each Register File Has Individual Write-Enable Controls and Address Lines

EN12

Abstract: EN13 SN74ALS870 SN74ALS870NT multibus ARCHITECTURE
Contextual Info: SN74ALS870 DUAL 16-BY-4 REGISTER FILES SDAS139A – DECEMBER 1982 – REVISED JANUARY 1995 • • • • • DW OR NT PACKAGE TOP VIEW 3-State Buffer-Type Outputs Drive Bus Lines Directly Each Register File Has Individual Write-Enable Controls and Address Lines

Contextual Info: SN74ALS870 DUAL 16-BY-4 REGISTER FILES SDAS139A – DECEMBER 1982 – REVISED JANUARY 1995 • • • • • DW OR NT PACKAGE TOP VIEW 3-State Buffer-Type Outputs Drive Bus Lines Directly Each Register File Has Individual Write-Enable Controls and Address Lines