RAS 1215 Search Results

jeida dram 88 pin

Contextual Info: IB M 1 1 J 4 3 2 0 C N 4M x 32 3.3V IC DRAM Card Features • Industry Standard 88Pin IC DRAM Card • Performance: Single 3.3V, ± 0.3V Power Supply All inputs buffered except RAS and DATA inputs Multiple RAS inputs for x16 or x32 selectability 12/10 Addressing Row/Column

TB 1226 BN

Abstract: 531 T70 n03 0AS001 B05AD 2U 34
Contextual Info: in y Intel 450NX PCIset 82454NX PCI Expander Bridge PXB 82453NX Data Path Multiplexor (MUX) 82452NX RAS/CAS Generator (RCG) 82451 NX Memory & I/O Controller (MIOC) Revision 1.3 March 1999 Intel Corporation 1998,1999 Information in this document is provided in connection with Intel products. No license, express or

INTEL 450NX

Abstract: intel 8042 8042 intel kbc intel G31 circuit diagram LXG Series DIODE C04 06 intel 8042 port 64h pciset datasheet transistor w04 450GX
Contextual Info: intel  Intel 450NX PCIset 82454NX PCI Expander Bridge PXB 82453NX Data Path Multiplexor (MUX) 82452NX RAS/CAS Generator (RCG) 82451NX Memory & I/O Controller (MIOC) Revision 1.3 March 1999 Intel Corporation 1998, 1999 Information in this document is provided in connection with Intel products. No license, express or

intel 8042

Abstract: 450GX 450NX 82451NX 82452NX 82453NX 82454NX CL-CK L10
Contextual Info: intel  Intel 450NX PCIset 82454NX PCI Expander Bridge PXB 82453NX Data Path Multiplexor (MUX) 82452NX RAS/CAS Generator (RCG) 82451NX Memory & I/O Controller (MIOC) Order Number: 243771-004 June 1998 Intel Corporation 1998 Information in this document is provided in connection with Intel products. No license, express or

5962-7802301MEX

Abstract: 5962-7802301MFX 5962-7802301M2X qml-38535 smd marking 6z 26f31 smd marking code 6z 7802301EX
Contextual Info: AMO ¿I NOTICE OF REVISION NOR (See MIL-STD-480 fo r instru ctio n s) Th's re visio n aescriseo aelaw ras seen autnor'zea fa r tre ascunent ''s te o . DATE ( vYMP00i 31/11/22 conn AccrcvBO 0MB No. :704-0188 Public re so rtin g Buraen fo r th is c o lle c tio n Is estimated to average 1 hour cer -esponse. inclu d in g tne time fo r reviewing

ry 130-2

Contextual Info: APPLICA TION NOTE \ NEC DRAM-CPU CONNECTION METHODS \ \ NEC Corporation 1994, 1996 \ \ Document No. M11443EJ3V0AN00 3rd edition (Previous No. IEA-1302) Date Published August 1996 P Printed in Japan 1215 The application circuits and their parameters are for reference only and are not intended for use in actual design-ins.

CXP10

Contextual Info: '3 * -W molate 2S6K x 8 CMOS Vìdeo RAM MVM8256X-10/12/15 Issue 1.2 : January 1993 S e m ic o n d u c to r ADVANCE PRODUCT INFORMATION Inc. ^ 262,144 x 8 CMOS Video RAM N < ckage Type - Features >< Pin Definition 40 GND1 SI/07 SI/06 37 Sl/05 36 SI/04 35 SE

Contextual Info: DATA SHEET NEC / MOS INTEGRATED CIRCUIT / ¿¿PD42S 16165L , 4 2 16 16 5 L 3.3 V OPERATION 16 M-BIT DYNAMIC RAM 1 M-WORD BY 16-BIT, HYPER PAGE MODE EDO , BYTE READ/WRITE MODE D e s c rip tio n The /iP D 42S 16165L, 4216165L are 1,048,576 words by 16 bits CMOS dynam ic RAMs with optional hyper page

Contextual Info: ADVANCE MT4 L C2M8B1/2 2 MEG X 8 WIDE DRAM |^ IIC = R O N WIDE DRAM 2 MEG x 8 DRAM 5.0V FAST-PAGE-MODE (MT4C2M8B1/2) 3.0/3.3V, FAST-PAGE-MODE (MT4LC2M8B1/2) FEATURES PIN ASSIGNMENT (Top View) OPTIONS MARKING • Timing 60ns access 70ns access 80ns access -6

Contextual Info: ADVANCE MT4 L C2M8A1/2 S 2 MEG x 8 DRAM I^IICRON 2 MEG x 8 DRAM 5.0V, SELF REFRESH (MT4C2M8A1/2 S) 3.0/3.3V, SELF REFRESH (MT4LC2M8A1/2 S) FEATURES PIN ASSIGNMENT (Top View) • SELF REFRESH, i.e. "Sleep Mode" • Industry standard x8 pinouts, timing, functions and

Contextual Info: ADVANCE MT4 L C2M8B1/2 S 2 MEG X 8 WIDE DRAM M ICRO N WIDE DRAM 2 MEG X 8 DRAM 5.0V SELF REFRESH ÍMT4C2M8B1/2 S) 3.0/3.3V, SELF REFRESH (MT4LC2M8B1/2 S) FEATURES PIN A SSIG N M EN T (Top View) OPTIONS MARKING • Timing 60ns access 70ns access 80ns access

Contextual Info: ADVANCE MT4 L C2M8A1/2 2 MEG X 8 WIDE DRAM M IC R O N WIDE DRAM 2 MEG X 8 DRAM 5.0V, FAST-PAGE-MODE (MT4C2M8A1/2) 3.0/3.3V, FAST-PAGE-MODE (MT4LC2M8A1/2) FEATURES PIN ASSIGNMENT (Top View) OPTIONS MARKING • Timing 60ns access 70ns access 80ns access -6 -7

Contextual Info: H I T A C H I / L O G I C / A R R A Y S / n SIE D 4 4 ^ 5 0 3 o o n s o a HM538123 Series-131,072-Word X 8-Bit Multiport CMOS Video RAM T - HITE 400 4 6 - 2 3 - Z b • DESCRIPTION The HM538123 is a 1-Mbit multiport video RAM equipped with a 128k-word x

Contextual Info: I ADVANCE M T4 L C 2M 8B 1/2 S IEG X 8 W IDE DRAM MICRON WIDE DRAM 2 MEG X 8 DRAM 5.0V SELF REFRESH (MT4C2M8B1/2 S) 3.0/3.3V, SELF REFRESH (MT4LC2M8B1/2 S) FEATURES PIN ASSIGNMENT (Top View) OPTIONS 28 ] Vss 27 ] 0 Q 8 26 ] DQ7 Vcc [ 1 001 C 2 OQ2 [ 3 DQ3 [ 4

Contextual Info: ADVANCE M T4 L C 2M 8B 1/2 2 MEG X 8 W ID E DRAM I^ IIC R D N WIDE DRAM 2 MEG x 8 DRAM 5.0V FAST-PAGE-MODE (MT4C2M8B1/2) 3.0/3.3V, FAST-PAGE-MODE (MT4LC2M8B1/2) FEATURES PIN ASSIGNMENT (Top View) OPTIONS MARKING • Timing 60ns access 70ns access 80ns access

Contextual Info: ADVANCE MT4 L C2M8B1/2 2 MEG X 8 DRAM |U |IC =R O N 2 MEG x 8 DRAM 5.0V FAST PAGE M ODE (MT4C2M8B1/2) 3.0/3.3V, FAST PAGE M ODE (MT4LC2M8B1/2) FEATURES PIN ASSIGNMENT (Top View) • Industry standard x8 pinouts, timing, functions and packages • Address entry: 11 row, 10 column addresses (32ms);

dram zip

Contextual Info: PRELIMINARY U | | C n D N 256K X M T4C 16260/1 16 W ID E DRAM 256K X 16 DRAM WIDE DRAM ASYMMETRICAL, FAST-PAGE-MODE FEATURES • Industry-standard x l6 pinouts, timing, functions and packages • Address entry: ten row-addresses, eight columnaddresses • High-performance CMOS silicon-gate process

Contextual Info: ADVANCE l^ iic n o N 256K WIDE DRAM X MT4C16270/1 16 WIDE DRAM 256K x 16 DRAM FEATURES • Industry-standard xl6 pinouts, timing, functions and packages • High-performance CMOS silicon-gate process • Single +5V ±10% power supply • Low power, 3mW standby; 500mW active, typical

ras 1210

Abstract: ras- 1210
Contextual Info: ADVANCE MT4LC2M8B1 S MEG X 8 DRAM M IC R O N 2 DRAM 2 MEG x 8 DRAM 3.3V FAST PAGE MODE, OPTIONAL SELF REFRESH PIN ASSIGNMENT (Top View) • JEDEC- and industry-standard x8 pinouts, timing, functions and packages • High-performance CM OS silicon-gate process

pin diagram for IC cd 1619 cp

Abstract: pin configuration of IC 1619 cp 8A4A6 pin configuration of cd 1619 cp
Contextual Info: STI804100D2 168-PIN DIMMS 4M X 80 DRAM DIMM Memory Module FEATURES • GENERAL DESCRIPTION Performance range: *RAC ^CAC Vc STI804100D2-60 60ns 20ns 110ns STI804100D2-7Q 70ns 25ns 130ns The Simple Technology STI804100D2 is an 4M x 30 bit Dynamic RAM high density memory module. The module consist of 20

Contextual Info: PRELIMINARY I^ IIC R O N 256K WIDE DRAM 256K X X MT4C16260/1 16 WIDE DRAM 16 DRAM ASYMMETRICAL, FAST-PAGE-MODE FEATURES • Industry-standard x l6 pinouts, timing, functions and packages • Address entry: ten row-addresses, eight columnaddresses • High-perform ance CM OS silicon-gate process

Contextual Info: MICRON SEMICONDUCTOR INC b3E D • blllSM'î D D 0 7 7 H C1 lûl ■ MRN ADVANCE M IC R O N I MT4 L C2 M8 B112 2 MEG X 8 WIDE DRAM SEMICONDUCTOR INC WIDE DRAM 2 MEG x 8 DRAM 5.0V FAST-PAGE-MODE (MT4C2M8B1/2) 3.0/3.3V, FAST-PAGE-MODE (MT4LC2M8B1/2) FEATURES

Contextual Info: ADVANCE MT4 L C2M8A1/2 2 MEG X 8 DRAM M IC R O N 2 MEG x 8 DRAM 5.0V, FAST PAGE MODE (MT4C2M8A1/2) 3.0/3.3V, FAST PAGE MODE (MT4LC2M8A1/2) FEATURES PIN ASSIGNMENT (Top View) • Industry standard x8 pinouts, timing, functions and packages • Address entry: 12 row, nine column addresses (64ms)

Contextual Info: PRELIMINARY M IC R O N 256K WIDE DRAM X MT4C16260/1 16 WIDE DRAM 256K X 16 DRAM FEATURES • Industry-standard x l6 pinouts, timing, functions and packages • A ddress entry: ten row-addresses, eight columnaddresses • High-performance CMOS silicon-gate process