RAMS Search Results

Contextual Info: TM4164EC4 65,536 BY 4-BIT DYNAMIC RAM MODULE NOVEMBER 1983 - REVISED NOVEMBER 1985 SINGLE-IN-UNE PACKAGE 6 5 ,5 3 6 X 4 Organization TOP VIEW Single 5-V Supply (10% Tolerance) 22-Pin Single-in-Line Package (SIP) Utilizes Four 64K Dynamic RAMs in Plastic

D425G

Abstract: ACT21 SN74BCT2166
Contextual Info: SN74BCT2163, SN74BCT2164, SN74BCT2166 16K x 5 CACHE ADDRESS COMPARATORS/TAG RAMs SCHS012-D3513, JUNE 1990-REVISED NOVEMBER 1991 SN74BCT2163, SN74BCT2164 Fast Address to MATCH Delay. 12 ns Max FM PACKAGE CTOP VIEW ’BCT2163 Has Totem-Pole Match Output Q\*~

a14 Transistor

Contextual Info: TEXAS XNSTR QbE D | 011.1751 0075454 5 | SM61CD64, SMJ61CD64 65.536-W0RD BY 1-BIT STATIC RAMS Separate I/O J D PA C K A G E TOP VIEW AOC A1C A2C A3Q A4Q A5Q A6^ Military Temperature Range . . . -5 5 ° C to 125°C (M Suffix) • • Fast Static Operation

Contextual Info: TM S4500A DYNAMIC RAM CONTROLLER D 2 6 7 4 . JA N U A R Y 1982 TM S 4500A Controls Operation of 8K, 16K, 32K , and 64 K Dynam ic RAMs CLK ROY One Package Contains Address M ultiplexer, Refresh Control, and Timing Control • RENI CS ALE Directly Addresses and Drives Up to 2 5 6 K

SCAD002

Abstract: BCT2164
Contextual Info: SN74BCT2163, SN74BCT2164, SN74BCT2166 16K x 5 CACHE ADDRESS COMPARATORS/TAG RAMs _ D3513, JUNE 1990 — REVISED A U G U S T 1990 • Fast Address to MATCH Delay . . .12-ns Max • ’BCT2163 has Totem-Pole Match Output

Contextual Info: SM 64C16, SM J64C16 4096 WORD BY 4-BIT STATIC RAMS MARCH 1 98 7 —REVISED NOVEMBER 1987 Common I/O JO PACKAGE TOP VIEW • Military Temperature Range . . . - 5 5 ° C to 125°C (M Suffix) • Fast Static Operation • Battery Back-Up Operation . . . 2-Volt Data

Contextual Info: TM4256FL8, TM4256GU8 262,144 BY 8 BIT DYNAMIC RAM MODULES OCTOBER 1985 —REVISED FEBRUARY 1988 2 6 2 ,1 4 4 x 8 Organization TOP VIEW Utilizes Eight 256K Dynamic RAMs in Plastic Chip Carrier vss DQ3 A4 A5 DQ4 A6 A7 DQ5 A8 NC NC DQ6 W Long Refresh Period . . . 4 ms (25 6 Cycles)

TRW J500

Abstract: k45752 52S marking
Contextual Info: DATA SHEET NEC / MOS INTEGRATED CIRCUIT _ / /¿PD42S4260L, 424260L 3.3 V OPERATION 4 M-BIT DYNAMIC RAM 256 K-WORD BY 16-BIT, FAST PAGE MODE, BYTE READ/WRITE MODE Description The fiPD42S4260L, 424260L are 262 144 words by 16 bits dynamic CMOS RAMs. The fast page mode and

Contextual Info: SN74ACT2158, SN74ACT2159 8K x 9 CACHE ADDRESS COMPARATORS/DATA RAMs D 3 2 8 1 , M A Y 1 9 9 0 R E V IS E D J U N E 1990 Fast Address to MATCH Delay 22 ns Max FN PACKAGE TOP VIEW 8K x 10 Internal Static RAM ISCI 5 Ä • Word Reset Function for Single Entry

74ALS6302

Abstract: la 7184 74ALS6301 M 6302 XP 74als630
Contextual Info: SN74ALS6301, SN74ALS6302 DYNAMIC MEMORY CONTROLLERS D 2 9 0 0 . JA N U A R Y 1 9 8 6 —REVISED M A R C H 1 9 8 8 Provides Control for 16K, 64K. 256K, and 1M Dynamic RAMs SN 74ALS6301, S N 7 4A LS 6 30 2 . . Highest-Order Two-Address Bits Select One of Four Banks of RAMs

cxk5863b

Abstract: CXK5863BM
Contextual Info: SONY CXK5863BP/BM/BJ -25/30/35 8192-word x 8-bit High Speed CMOS Static RAM D escription CXK5863BP 28 pin DIP Plastic CXK5863BP/BM/BJ are 65,536 bits high speed CMOS static RAMs organized as 8,192 words by 8-bit and operate from a single 5V supply. These devices are

Contextual Info: * SY10/100/101480-6 SY10/100/101480-8 SY10/100/101480-10 16K x 1 EC L RAM SYNERGY S E M IC O N D U C TO R DESCRIPTION FEATURES • Address access time, tAA: 6/8/10ns max. ■ Chip select access time, tAC: The Synergy SY10/100/101480 are 16384-bit Random Access Memories RAMs , designed with advanced Emitter

L-10W

Contextual Info: Ordering number : ENÍK4663 Asynchronous Silicon Gate CMOS LSI no* 4663 SAXYO 11_ LC36256AL, AML-70W/85W/10W/12W li 256 K 32768 words x 8 bits SRAM Preliminary Overview Package Dimensions The LC36256AL, AML-70W/85W/10W/12W are fully asynchronous silicon gate CMOS static RAMs with an

TT104

Contextual Info: - i I O rdering n u m b e r:EN 3929A SANYO SEMICONDUCTOR CORP S3E D N0.3929A TTTTDTb OQlOlll blS M T S A J LC36257P, PL, PM, PML CMOS LSI SA\YO 256 Kbit 32768 x 8 CMOS Static RAM i PINOUT OVERVIEW LC36257P series devices are silicon-gate, CMOS static RAMs configured as 32 768 x 8 bits. They incorporate

as15 G

Abstract: AS15 G IC AS15 U AS15 f ic as15 LC3516A-15 LC3516AL LC3516AM as15 h as15- f
Contextual Info: F No.2360 A sy n c h ro n o u s'S ilic o n Gate CMOS LSI r i LC3516A,AM,AS/LC3516flL• AML.AS I 2048 W o rd s x 8 B its CMOS S ta tic RAMs - LC3516A series are fully asynchronous silicon gate CMOS static RAMs orga­

Contextual Info: RENESAS LSIs 2003.08.21 Ver. 7.0 M5M5V416CWG -55HI, -70HI 4194304-BIT 262144-WORD BY 16-BIT CMOS STATIC RAM DESCRIPTION FEATURES The M5M5V416CWG is a f amily of low v oltage 4-Mbit static RAMs organized as 262144-words by 16-bit, f abricated by Renesas's

FT6163

Contextual Info: FT6163/FT6163L  Ultra High Speed 8K x 9 Static Cmos Rams FEATURES Data Retention with 2.0V Supply, 10 µA Typical Current 7163L Military) Common I/O Fully TTL Compatible Inputs and Outputs Standard Pinout (JEDEC Approved)

10ST10

Abstract: lq55
Contextual Info: Ordering n u m b e r:EN4794B CMOS LSI LC3564S, SS, SM, ST-70/85/10 64K 8192wordsX8 bits SRAM Overview The LC3564S, LC3564SS, LC3564SM, and LC3564ST are asynchronous silicon gate CMOS static RAMs with an 8192-word X 8-bit organization. These RAMs are full CMOS type

LH5116H

Contextual Info: LH5116/H C M O S 16K 2 K x 8 S tatic RAM FEATURES DESCRIPTION • 2,048 x 8 bit organization The LH5116/H are static RAMs organized a s 2 ,0 4 8 x 8 bits. It is fabricated using silicon-gate CMOS process technology. It features high speed access in read mode

idt7134

Abstract: CY7C1342 CY7C135
Contextual Info: fax id: 5203 ,.V.Ï.Ï.V.^ y nr' C Y 7C 135 Æ C Y p R E S S C Y 7C 1342 4K x 8 Dual-Port Static RAMs and 4K x 8 Dual-Port Static RAM with Semaphores Features True Dual-Ported memory cells which allow sim ulta­ neous reads of the sam e memory location 4K x 8 organization

dallas ds1213

Abstract: DS1213 8 pin DS1213 DS1213 DALLAS DS1213 smart socket rde 090 dallas ds1213 C Lithium Battery Protection Circuit for Battery P silr
Contextual Info: !? D a lla s S e m ic o n d u c to r S m a rtS o c k e t 1 6 /6 4 K DS1213 FEATURES P IN C O N N E C T IO N S • Accepts standard 2 K x 8 and 8K x 8 CMOS sta tic RAMs [“ □¡ ^ D2 □ 2 ¡e&Hv 2 8 O -i 27n cc 27 □ j • Embedded lithiu m energy cell retains

F16K

Abstract: 96LS42DC 96LS42DM 96LS42PC 96LS42
Contextual Info: 96LS42 C O N N E C T IO N D IA G R A M P IN O U T A 96LS42 r ADDRESS MULTIPLEXER/REFRESH COUNTER For 16K D ynam ic RAMs \ c p D E S C R IP T IO N — T h e 96LS42 is an address m u ltip le x e r and refre sh co u n te r fo r m u ltip le x e d address d y n a m ic RAM s re q u irin g refre sh of 64 o r 128 cycles.

1S26

Abstract: P4C116 P4C116L AD5e
Contextual Info: PERFORMANCE SEMICONDUCTOR SDE V • 7 0 b 2 5 cl7 0001780 3äb * P S C P4C116/P4C116L ULTRA HIGH SPEED 2K x 8 STATIC CMOS RAMS RAMS FEATURES ■ Full CMOS, 6T Cell Single 5V±10% Power Supply ■ High Speed (Equal Access and Cycle Times) -12,15/20/25/35 ns (Commercial)

SSSB

Contextual Info: HO» Pago 0001 01/16/89 11:19:17 Tx: AM27S07 - Ft: AMO FMT Am27S07 E 64-Bit Noninverting-Output Bipolar RAM DISTINCTIVE CHARACTERISTICS • • Fully decoded 16-word x 4-bit tow power Schottky RAMs Internal ECL circuitry for optimum speed/power perfor­ mance over voltage and temperature