RAM64K36
Abstract: wd19 RD23 RAM256X9 WD21
Contextual Info: A pp l i c a t i o n N o t e A C 1 7 7 Implementing Multi-Port Memories in Axcelerator Devices I n tro du ct i on This application note describes a user configurable VHDL wrapper for implementing dual-port and quad-port memory structures using a small number of programmable logic tiles
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128x36256x18512x9ram64k36+4wd19rd23ram256x9wd21
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RAM EDAC SEU
Abstract: SRAM edac AC304 sram 2114 edac 2114 SRAM RAM SEU RAM64k36 7 bit hamming code hamming code
Contextual Info: Application Note AC304 Simulating SEU Events in EDAC RAM Introduction The Actel RTAX-S Field Programmable Gate Array FPGA provides embedded user static RAM in addition to single-event-upset (SEU)-enhanced logic, including embedded triple-module redundancy (TMR)
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ac304ram edac seusram edacsram 2114+6edac2114 sramram seuram64k367 bit hamming codehamming code
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RAM64K36
Abstract: RAM64K36P 54SX-S MXT 276 BBUF RAM64 20/FIFO64K36
Contextual Info: Macro Library Guide June 2002 R1-2002 For more information about Actel’s products, call 888-99-ACTEL or visit our Web site at http://www.actel.com Actel Corporation • 955 East Arques Avenue • Sunnyvale, CA USA 94086 U.S. Toll Free Line: 888-99-ACTEL • Customer Service: 408-739-1010 • Customer Service FAX: 408-522-8044
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r1-2002888-99-actelram64k36ram64k36p+554sx-smxt 276bbufram6420/fifo64k36
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