RAM Search Results

Contextual Info: TC55417P/J —15H. TC55417P/J-20H TC55417P/J—25H. TC55417P/J-35H • * 16,384 W O R D x 4 BIT CMOS STATIC RAM DESCRIPTION The TC55417P/J—H is a 65,536 bit high speed static random access memory organized as 16,384 words by 4 bits using CMOS technology, and operated from a single 5 - volt supply.

i486

Contextual Info: SN74BCT2141 2-WAY 8K x 18 SYNCHRONOUS CACHE DATA RAM D3613. A UG UST 1990 2-Way 8K x 18 Bit Architecture FN PACKAGE TOP VIEW Synchronous Read and Write Access at 50 MHz Clock Frequency Incorporates Burst Counter for Burst-Read (Read-Hit) Cycles or Burst-Write (Line-Fill)

A9RV

Abstract: 5s a315 A327
Contextual Info: TOSHIBA TC514900AJLL-70/80 524,288 WORD X 9 BIT DYNAMIC RAM DESCRIPTION The TC514900AJLL is the new generation dynamic RAM organized 524,288 word by 9 bit. The TC514900AJLL utilizes Toshiba’s CMOS silicon gate process technology as well as advanced circuit

dg1u

Abstract: TLP624
Contextual Info: TLP624,-2,-4 GaAs IRED a PHOTO-TRANSISTOR TLP6 24 PRO G RAM M ABLE CONTROLLERS AC /DC-INPUT M ODULE TELECOM M UNICATIO N The TOSHIBA TLP624, -2 and -4 consist of a gallium arsenide infrared emitting diode optically coupled to a photo-transistor. The TLP624-2 offers two isolated channels in an eight lead plastic

MG50G2CL3

Abstract: Mg50G2cl mg50g2
Contextual Info: GTR MODULE SILICON NPN TRIPLE DIFFUSED TYPE MG50G2CL3 HIGH POWER SWITCHING APPLICATIONS. Unit in ram MOTOR CONTROL APPLICATIONS. FEATURES : . The Collector Is Isolated from Case. . 2 Power Transistors and 2 Free Wheeling Diodes are Built-In to 1 Package. . High DC Current Gain: hFE=100 Min. (Ic=50A)

260-pin

Contextual Info: TOSHIBA TC55V1864J/FT-10/12/15 PRELIMINARY SILICON GATE CMOS 65,536 WORD x 18 BIT CMOS STATIC RAM Description TheTC55V1864J/FT is a 1,179,648 bit high speed CMOS static random access memory organized as 65,536 words by 18 bits and operated from a single 3.3V : upply. Toshiba’s advanced CMOS technology and circuit design enable high speed operation.

4A04I

Abstract: tc514100a
Contextual Info: TC51441OAP/AJ/ASJ/AZ—70, TC51441OAP/AJ/ASJ/AZ-80 TC51441OAP/AJ/ASJ/AZ-10 PRELIMINARY 1,048,576 W ORD x 4 BIT DYNAMIC RAM DESCRIPTION The TC51441 OAP/AJ/ASJ/AZ is the new generation dynamic RAM organized 1,048,576 words by 4 bits. The TC514410AP/AJ/ASJ/AZ utilizes TOSHIBA’S CMOS Silicon gate process technology as well as

Contextual Info: • ■ ! ■ ■ ■ ■ • '|<f TOSHIBA MIOS MEMORY PRODUCTS 8,192 WORD X 8 BIT CM OS STATIC RAM SILICON GATE C M O S T C 5 5 63 A P L-1 0, T C 5563A P L-12 T C 55 6 3 A P L -1 5 DESCRIPTIO N The TC5563APL is 65,536 bit static random access memory organized as 8,1 92 words by 8 bits

BE423

Contextual Info: TOSHIBA TC5118325BJ/BFT-70 PRELIMINARY 524,288 WORD X 32 BIT EDO DYNAMIC RAM Description The TC5118325BJ/BFT is the Hyper Page Mode (EDO) dynamic RAM organized 524,288 words by 32 bits. The TC5118325BJ/BFT utilizes Toshiba’s CMOS silicon gate process technology as well as advanced circuit techniques to pro­

TC514170BJ-80

Abstract: tc514170 TC514170BJ80
Contextual Info: TOSHIBA TC514170BJ-70/80 262,144 WORD X 16 BIT DYNAMIC RAM DESCRIPTION The TC514170BJ is the new generation dynam ic RAM organized 262,144 word by 16 bit. The TC514170BJ utilizes T oshiba’s CM OS silicon gate process technology as well as advanced circuit techniques

TM4SN64EPN10

Abstract: TM2SN64EPN-10 TM48N64EPN TM4SN64EPN-10 TMS626812
Contextual Info: TM2SN64EPN 2097152 BY 64-BIT TM4SN64EPN 4194304 BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULES _ SYNCHRONOUS CLOCK CYCLE TIME *CK3 , {CL = 3 t ACCESS TIME CLOCK TO OUTPUT >CK2 CL = 2) *CK3 (CL = 3) *CK2 (CL = 2) • • • • • • • •

Contextual Info: TM4164EC4 65,536 BY 4-BIT DYNAMIC RAM MODULE NOVEMBER 1983 - REVISED NOVEMBER 1985 SINGLE-IN-UNE PACKAGE 6 5 ,5 3 6 X 4 Organization TOP VIEW Single 5-V Supply (10% Tolerance) 22-Pin Single-in-Line Package (SIP) Utilizes Four 64K Dynamic RAMs in Plastic

wc 2c

Contextual Info: SMJ4416 16.384-WORD BY 4-BIT DYNAMIC RAM AUGUST 1980 JO PACKAGE 1 6 ,3 8 4 x 4 O rg anizatio n TO P V IE W S ingle 5 -V S u p p ly ( ± 1 0 % T olerance) g P erfo rm a nce Ranges ACCESS T IM E • DQ1 C C2 DQ 2C Ul8 Dvss 17 3 D Q 4 3 16 4 15 "2C A S "2D Q 3

TC5117445CSJ

Contextual Info: TO SHIBA_ TC5117445CSJ-40,-50,-60 TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC 4,194,304-WORD BY 4-BIT EDO HYPER PAGE DYNAMIC RAM DESCRIPTION The TC5117445CSJ is an EDO (Hyper Page) dynamic RAM organized as 4,194,304 words by 4 bits. The

TC5117800bnt-60

Abstract: TC5117800B
Contextual Info: TOSHIBA TC5117800BNJ/BNT-60/70 PRELIMINARY 2,097,152 WORD X 8 BIT FAST PAGE DYNAMIC RAM Description The TC5117800BNT is the fast page dynamic RAM organized 2,097,152 words by 8 bits. The TC5117800BNT utilizes Toshiba’s CMOS silicon gate process technology as well as advanced circuit techniques to provide wide operating margins,

82C8167

Abstract: UM82C8167 UM82C8
Contextual Info: UMC UM82C8167 S S 2 S S S 2 S 2 Î Real-Time Clock RTC eatures Microprocessor compatible (8-bit data bus) Milliseconds through month counters 56 bits of RAM with comparator to compare the real time counter to the RAM data 2 IN TERRU PT OUTPUTS with 8 possible interrupt

Contextual Info: TO SHIBA THMY644071EG-10 TENTATIVE TOSHIBA HYBRID DIGITAL INTEGRATED CIRCUIT 4,194,304-WORD BY 64-BIT SYNCHRONOUS RAM MODULE DESCRIPTION The THMY644071EG is a 4,194,304-word by 64-bit synchronous dynamic RAM module consisting of four TC59S6416FT RAMs and an unbuffer on a printed circuit board.

TC528257

Abstract: n724
Contextual Info: TOSHIBA SILICON GATE CMOS TC528257 t a r g e t s p e c 262,144WORDS X 8BITS MULTIPORT RAM DESCRIPTION The TC528257 is a 2M bit CM OS multiport m em ory equipped with a 262,144-w ords by 8 -bits dynam ic random access m em ory RAM port and a 512-words by 8 -bits static serial access m emory (SA M ) port. The

Contextual Info: TM4EP72BPB, TM4EP72BJB, 4194304 BY 72-BIT TM4EP72CPB, TM4EP72CJB 4194304 BY 72-BIT EXTENDED-DATA-OUT BUFFERED DYNAMIC RAM MODULES _ _ • • • • Long Refresh Periods: - TM4EP72CxB: 64 ms 4096 Cycles

Contextual Info: PRELIMINARY 4,194,304 WORD x 1 BIT DYNAMIC RAM DESCRIPTION The TC514101AP/AJ/ASJ/AZ is the new generation dynamic RAM organized 4,194,304 words by 1 bit. The TC514101AP/AJ/ASJ/AZ utilizes TOSHIBA’S CMOS Silicon gate process technology as well as advanced circuit techniques to provide wide operating m argins, both internally and to the system user.

TC514265DJ

Abstract: TC514265D TC514265 SOJ40-P-400
Contextual Info: TOSHIBA TC514265DJ/DFT-50/60/70 PRELIMINARY 262,144 WORD X 16 BIT EDO HYPER PAGE DYNAMIC RAM Description TheTC514265DJ/DFT is an EDO (hyper page) dynamic RAM organized as 262,144 words by 16 bits. TheTC514265DJ/ DFT utilizes Toshiba's CMOS silicon gate process technology as well as advanced circuit techniques to provide wide oper­

Contextual Info: TOSHIBA TC514800AJ/AZ/AFT-70/80 524,288 WORD X 8 BIT DYNAMIC RAM DESCRIPTION The TC514800AJ/AZ/AFT is the new generation dynam ic RAM organized 524,288 word by 8 bit. The TC514800A J/AZ/AFT utilizes T oshiba’s CM OS silicon gate process technology as w ell as advanced circuit

Contextual Info: SILICON NPN EPITAXIAL TYPE PCT PROCESS 2SC3671 ST0R0B0 FLASH APPLICATIONS. MEDIUM POWER AMPLIFIER APPLICATIONS. Unit in ram . High DC Current Gain and Excellent hFE Linearity : hFE(l)=140~450 (VCE=2V, : h F E(2)=70(Min.) Ic =0.5A) (VC E=2V, IC=4A) . Low Saturation Voltage

Contextual Info: TOSHIBA TC55V1664J/FT-10/12/15 PRELIMINARY SILICON GATE CMOS 65,536 WORD x 16 BIT CMOS STATIC RAM Description The TC55V1664J/FT is a 1,048.5,'6 bit high speed CMOS static random access memory organized as 65,536 words by 16 bits and operated from a single 3.3V sjpply. Toshiba's advanced CMOS technology and circuit design enable high speed operation.