RAAW Search Results

SN54LV14

Abstract: 2020CN
Contextual Info: SN54LV14, SN74LV14 HEX SCHMITT-TRIGGER INVERTERS _ S C L S 1 8 7 B - FEBRUARY 1 9 9 3 - REVISED APRIL 1996 EPIC Enhanced-Performance Implanted CMOS 2-|i Process SN54LV14 . . . J OR W PACKAGE SN74LV14. . . D, DB, OR PW PACKAGE (TOP VIEW) TVplcal V q l p (Output Ground Bounce)

Contextual Info: SN54LVTH162240, SN74LVTH162240 3.3-V ABT 16-BIT BUFFERS/DRIVERS WfTH 3-STATE OUTPUTS SCBS665B - MARCH 1997 - REVISED SEPTEMBER 1997 • • • • • • • • • • • • Members of the Texas Instruments Widebu£u Family State-of-the-Art Advanced BiCMOS

Contextual Info: HD64180S -NPU Network Processing Unit • DESCRIPTION The HD64180S, network processing unit (N PU ), provides multipurpose high-speed com m unication control functions on a single LSI chip. The HD64180S offers high perform ance com m unication protocol process­

MT28F400B1

Contextual Info: *V K p i i c z R a f s j v O O i B!. i ' * f FLASH MEMORY m a r tV o lt a g e PIN ASSIGNMENT Top View 44-Pln SOP » Seven erase blocks: 16KB/8K-word boot block (protected) Two 8KB /4K-word param eter blocks Four main memory blocks • SmartVoltage Technology (SVT):

Contextual Info: E2G 1 054-18-62 O K I Semiconductor MD56V62800A 4-Bank x 2,097,152-Word x 8-Bit SY N C H R O N O U S DYNAMIC RAM DESCRIPTION The MD56V62800A is a 4-bank x 2,097,152-word x 8-bit synchronous dynamic RAM, fabricated in Oki's CMOS silicon-gate process technology. The device operates at 3.3 V. The inputs and

ADC0S04

Abstract: ADC0802 adc0804 national semiconductor j60 mic 256R ADC0801 ADC0803 ADC0804 ADC0805 INS8080A
Contextual Info: ADC0801/ADC0802/ADC0803/ADC0804/ADC0805 ^National ÆÆ Semiconductor ADC0801/ ADC0802/ADC0803/ADC0804/ADC0805 8-Bit jitP Compatible A /D Converters General D escription The ADC0801, ADC0802, ADC0803, ADC0804 and . ADC0805 are CMOS 8-bit successive approximation A /D

Contextual Info: DO NOT SCALE THIS ORAW1NG REV ISIO N S SYM DATE E.C.O, NO. APPR. OFFICIAL ENG. RELEASE TO MFG. SEE NOTE 4. SEE NOTE 5. DESCRIPTION u V W REDESIGNED DET 10-7-8! i 35895 38016 ITEM 7 WAS 31-10059 1 ITEM 2 WAS 31-12003-1 4/1/91 8. R ED R A W N CHANGED PLATE NDTE lj REMOVED PLATE NOTES

HD63A21 equivalent

Contextual Info: H D 6 3 2 1 /H D 6 8 2 1 -PI A Peripheral In te rfa c e A d apter The HD6321/HD6821 Peripheral Interface Adapter provides the universal means of interfacing peripheral equipment to the HD6800 Microprocessing Unit (M PU ). This device is capablc

Contextual Info: Up/Down Counting Meter omRon K3NC Up/Down Counting Meter Operation Manual Produced January 1998 iv N o tic e : OMRON products are manufactured for use according to proper procedures by a qualified operator and only for the purposes described in this manual.

752E

Contextual Info: SN54HCT257, SN74HCT257 QUADRUPLE 2-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS WITH 3-STATE OUTPUTS _ SCLS072A- NOVEMBER 1968- REVISED MARCH 1996 Inputs Are TTL-Voltage Compatible Provide Bus Interface From Multiple

Contextual Info: SN54AHC540, SN74AHC540 OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCLS260C - DECEMBER 1995 - REVISED JUNE 1996 • • [ • • SN54AHC540 . . . J OR W PACKAGE SN74AHC540 . . . DB, DW, N, OR PW PACKAGE TOP VIEW Operating Range 2-V to 5.5-V Vcc EPIC'* (Enhanced-Performance Implanted

Contextual Info: TOSHIBA TENTATIVE TC59S6416FT/FTL-80,-10 TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC 1,048,576-WORDSX4BANKSX 16-BITS SYNCHRONOUS DYNAMIC RAM DESCRIPTION TC59S6416FT/FTL is a CMOS synchronous dynamic random access memory organized as 1,048,576words X 4 bank X 16 bits. Fully synchronous operations are referenced to the positive edges of clock

RAAW

Contextual Info: T O S H IB A TENTATIVE TC59S6432BFT/BFTL-80,-10 TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC 524,288-WORDS X4BANKSX 32-BITS SYNCHRONOUS DYNAMIC RAM DESCRIPTION TC59S6432BFT/BFTL is a CMOS synchronous dynamic random access memory organized as 524,288words X 4 banks X 32 bits.

Contextual Info: T O S H IB A TEN TA TIV E T C 5 9 G 1632AFB-80,-10.-12 T O SH IB A M O S D IG ITAL IN T EG R A T ED C IRC U IT SILICO N M O N O LITH IC 262,144-WORD x 2-BANK x 32-BIT SYN C H RO N O U S G RA PH IC S R A M DESCRIPTION The TC59G1632AFB is a CMOS synchronous graphics random access memory organized as 262,144

Contextual Info: I SN74LVC843 9-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS SC AS308A- MARCH 1993 - REVISED JULY 1995 DB, DW, OR PW PACKAGE TOP VIEW EP/C (Enhanced-Performance Implanted CMOS) Submicron Process Typical V qlp (Output Ground Bounce) < 0.8 V at Vcc = 3.3 V, TA = 25°C

str 4479

Contextual Info: TMS427800, TMS427800P 2 097152 WORD BY 8-BIT LOW VOLTAGE DYNAMIC RANDOM-ACCESS MEMORIES SMKS27&-JANUARY 1993 Organization. . . 2 097 152 x 8 Single 3.3-V Power Supply +0.3 V Tolerance Performance Ranges: DE PACKAGE* DZ PACKAGEt (TOP VIEW) (TOP VIEW) (tRAC) (tCAC)

Contextual Info: L427525 D042Ô7Ô bfl? • NECE NEC NEC Electronics Inc. fjPD78014Y Family fiPD78011BY/012BY/013Y/014Y/P014Y 8 ' Bit>K-Series Microcontrollers General Purpose With A/D Converter and I2C Bus Preliminary ber 1993

E64380

Abstract: CFC5 PC112L PC113L YDE0884 84859
Contextual Info: PCl 10L/PCl 1 lL/PCl 12L/PCl 13L PCl 10L/PCl 1 lL PCl 12L/PCl 13L Long Creepage Dietance Type Photocou*r M Lead feting ow II tj~] and bpi~ reel hp P OWI are alw available. iWllW/RlllU~PCl 12U/PCl13U, PCllW/KlllLPO/PCl 12LW/PCl13LW (Page 656) x DIN YDE0884 approvti ow is alw available as an option

MT42C4064

Contextual Info: MICRO N T E C H N O L O G Y INC 5SE D • D G 0 5 7 b b Mñb H M R N UiT42C4064 883C 1 Ô4K x 4 VRAM 1 |W |iC = R O S ! MILITARY VRAM 64K x 4 DRAM WITH 256 x 4 SAM PIN ASSIGNMENT (Top View • MIL-STD-883, Class B 24-Pin DIP (D-11) FEATURES • • •