QUAD 3 INPUT OR GATE Search Results

74ABT544

Contextual Info: Philips Semiconductors Functional selection guide ABT family GATES FUNCTION DEVICE NUMBER INVERTERS Hex inverter 74ABT04 NAND Quad 2 input 74ABT00 Triple 3 input 74ABT10 Dual 4 input 74ABT20 AND Quad 2 input 74ABT08 NOR Quad 2 input 74ABT02 OR Quad 2 input

SOP20

Abstract: SOL20 DIP20 DIP-20
Contextual Info: BiCMOS Standard Logics TD74BC Series A4 Typo No. Package Function TD74BC00P Quad 2-Input NAND Gate DIP14 TD74BC08P Quad 2-Input AND Gate DIP14 TD74BC32P Quad 2-Input OR Gate DIP14 TD74BC230P/F/FW Octal Bus Butter/Inverting and Non-lnvertlng/3-state DIP20/SOP20/SOL20

Contextual Info: 5 7 0 3 wo 5706 QUAD 2-INPUT PERIPHERAL/POWER DRIVERS -TRANSIENT-PROTECTED OUTPUTS These 16-lead quad 2-input peripheral/power drivers are bipolar monolithic integrated circuits containing AND or OR logic gates, highcurrent switching transistors, and transient-suppression diodes

intersil DATE CODE MARKING

Abstract: HCS32D HCS32DMSR HCS32HMSR HCS32K HCS32KMSR HCS32MS
Contextual Info: HCS32MS Data Sheet April 11, 2007 Radiation Hardened Quad 2-Input OR Gate FN3057.1 Features • 3 Micron Radiation Hardened SOS CMOS The Intersil HCS32MS is a Radiation Hardened Quad 2-Input OR Gate. A low on both inputs forces the output to a low state.

Contextual Info: HCS32MS Data Sheet April 11, 2007 Radiation Hardened Quad 2-Input OR Gate FN3057.1 Features • 3 Micron Radiation Hardened SOS CMOS The Intersil HCS32MS is a Radiation Hardened Quad 2-Input OR Gate. A low on both inputs forces the output to a low state.

Contextual Info: 4071B 4072B 4075B INTERNATIONAL, INC CMOS OR GATES 4071B - Quad 2-Input OR 4072B - Dual 4-Input OR 4075B - Triple 3-Input OR CONNECTION DIAGRAMS all packages FEATURES 4 ♦ ♦ Buffered Outputs Diode Protection on all Inputs Fully "B"-Series Compatible TRUTH TABLE

SELIC

Abstract: NLB6201
Contextual Info: NEL SELIC NLB6201 Quad 3 input OR/NOR Pin A ssignm ent Top View C eram ic Description The NLB6201 is an ultra high-speed monolithic quad 3-input OR/NOR gates. 01 01 D1a D1 b D1c D2a 18 17 n n n n n n Features • Typical AC characteristics Data rate up to 3.5 Gb/s.

TC4072BP

Abstract: TC4075BP TC4075 TC4072BF
Contextual Info: TC4071BP/BF, TC4072BP/BF, TC4075BP/BF C2M O S DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC TC4071BP/TC4071BF QUAD 2 INPUT OR GATE TC4072BP/TC4072BF DUAL 4 INPUT OR GATE TC4075BP/TC4075BF TRIPLE 3 INPUT OR GATE TC4071BP/BF, TC4075BP/BF and TC4072BP/BF are

4-DIGIT counter with 7-SEGMENT DISPLAY

Abstract: binary to hex led display decoder TC5000 tc5067 IC451 IC-451 tc4036 TC5066 TC4012 Multivibrator 555
Contextual Info: TC4000 Series PAGE FUNCTION PRODUCT NAME TC4000BP DUAL 3 INPUT NOR GATE PLUS INVERTER 75 TC4001BP/BF/BFN QUAD 2 INPUT N OR GATE 80 TC4001UBP QUAD 2 INPUT NOR GATE 83 TC4002BP/BF DUAL 4 INPUT NOR GATE 80 18-STAGE STATIC SHIFT REGISTER V ' ' 86 1/ "TC4006BP

Contextual Info: Data sheet acquired from Harris Semiconductor SCHS056D – Revised August 2003 CD4071B CD4072B CD4075B Quad 2-Input Dual 4-Input Triple 3-Input OR OR OR Gate Gate Gate H CD4071B, CD4072B, and CD4075B OR gates provide the system designer with direct implementation of the positive-logic OR

CD4071BF3A harris

Abstract: CD4072BE CD4071BE CD4071BEE4 CD4071BF CD4071BF3A CD4071BM 7706002CA CD4071B CD4071BM96
Contextual Info: Data sheet acquired from Harris Semiconductor SCHS056D – Revised August 2003 CD4071B CD4072B CD4075B Quad 2-Input Dual 4-Input Triple 3-Input OR OR OR Gate Gate Gate H CD4071B, CD4072B, and CD4075B OR gates provide the system designer with direct implementation of the positive-logic OR

CD4071BE

Contextual Info: Data sheet acquired from Harris Semiconductor SCHS056D – Revised August 2003 CD4071B CD4072B CD4075B Quad 2-Input Dual 4-Input Triple 3-Input OR OR OR Gate Gate Gate H CD4071B, CD4072B, and CD4075B OR gates provide the system designer with direct implementation of the positive-logic OR

Contextual Info: Data sheet acquired from Harris Semiconductor SCHS056D – Revised August 2003 CD4071B CD4072B CD4075B Quad 2-Input Dual 4-Input Triple 3-Input OR OR OR Gate Gate Gate H CD4071B, CD4072B, and CD4075B OR gates provide the system designer with direct implementation of the positive-logic OR

CD4071

Contextual Info: Data sheet acquired from Harris Semiconductor SCHS056B – Revised February 2003 CD4071B CD4072B CD4075B Quad 2-Input Dual 4-Input Triple 3-Input OR OR OR Gate Gate Gate H CD4071B, CD4072B, and CD4075B OR gates provide the system designer with direct implementation of the positive-logic OR

7706002CA

Abstract: CD4071B CD4071BE CD4071BF CD4071BF3A CD4071BM CD4071BM96 CD4071BM96E4 CD4072B CD4075B
Contextual Info: Data sheet acquired from Harris Semiconductor SCHS056D – Revised August 2003 CD4071B CD4072B CD4075B Quad 2-Input Dual 4-Input Triple 3-Input OR OR OR Gate Gate Gate H CD4071B, CD4072B, and CD4075B OR gates provide the system designer with direct implementation of the positive-logic OR

7706002CA

Abstract: CD4071B CD4071BE CD4071BEE4 CD4071BF CD4071BF3A CD4071BF3AS2534 CD4071BM CD4072B CD4075B
Contextual Info: Data sheet acquired from Harris Semiconductor SCHS056D – Revised August 2003 CD4071B CD4072B CD4075B Quad 2-Input Dual 4-Input Triple 3-Input OR OR OR Gate Gate Gate H CD4071B, CD4072B, and CD4075B OR gates provide the system designer with direct implementation of the positive-logic OR

Contextual Info: Data sheet acquired from Harris Semiconductor SCHS056D – Revised August 2003 CD4071B CD4072B CD4075B Quad 2-Input Dual 4-Input Triple 3-Input OR OR OR Gate Gate Gate H CD4071B, CD4072B, and CD4075B OR gates provide the system designer with direct implementation of the positive-logic OR

CD4071BE

Abstract: CD4075BE TSSOP 14 Package CD4071BPWR ACTIVE TSSOP 7706002CA CD4071B CD4071BF CD4071BF3A CD4071BM CD4071BM96 CD4071BMT
Contextual Info: Data sheet acquired from Harris Semiconductor SCHS056D – Revised August 2003 CD4071B CD4072B CD4075B Quad 2-Input Dual 4-Input Triple 3-Input OR OR OR Gate Gate Gate H CD4071B, CD4072B, and CD4075B OR gates provide the system designer with direct implementation of the positive-logic OR

Contextual Info: Data sheet acquired from Harris Semiconductor SCHS056B – Revised February 2003 CD4071B CD4072B CD4075B Quad 2-Input Dual 4-Input Triple 3-Input OR OR OR Gate Gate Gate H CD4071B, CD4072B, and CD4075B OR gates provide the system designer with direct implementation of the positive-logic OR

CD4075

Abstract: cd4071
Contextual Info: Data sheet acquired from Harris Semiconductor SCHS056B – Revised February 2003 CD4071B CD4072B CD4075B Quad 2-Input Dual 4-Input Triple 3-Input OR OR OR Gate Gate Gate H CD4071B, CD4072B, and CD4075B OR gates provide the system designer with direct implementation of the positive-logic OR

CD4071B

Abstract: CD4072B CD4075B MS-001 SCHS056D
Contextual Info: Data sheet acquired from Harris Semiconductor SCHS056D – Revised August 2003 CD4071B CD4072B CD4075B Quad 2-Input Dual 4-Input Triple 3-Input OR OR OR Gate Gate Gate H CD4071B, CD4072B, and CD4075B OR gates provide the system designer with direct implementation of the positive-logic OR

7706002CA

Abstract: CD4071B CD4071BE CD4071BEE4 CD4071BF CD4071BF3A CD4071BF3AS2534 CD4071BM CD4072B CD4075B
Contextual Info: Data sheet acquired from Harris Semiconductor SCHS056D – Revised August 2003 CD4071B CD4072B CD4075B Quad 2-Input Dual 4-Input Triple 3-Input OR OR OR Gate Gate Gate H CD4071B, CD4072B, and CD4075B OR gates provide the system designer with direct implementation of the positive-logic OR

cd4075

Abstract: CD4071 CD4072 CD4071B CD4072B CD4075B MS-001 "OR Gates"
Contextual Info: Data sheet acquired from Harris Semiconductor SCHS056B – Revised February 2003 CD4071B CD4072B CD4075B Quad 2-Input Dual 4-Input Triple 3-Input OR OR OR Gate Gate Gate H CD4071B, CD4072B, and CD4075B OR gates provide the system designer with direct implementation of the positive-logic OR

Contextual Info: Data sheet acquired from Harris Semiconductor SCHS056D – Revised August 2003 CD4071B CD4072B CD4075B Quad 2-Input Dual 4-Input Triple 3-Input OR OR OR Gate Gate Gate H CD4071B, CD4072B, and CD4075B OR gates provide the system designer with direct implementation of the positive-logic OR