QL8X12A Search Results

Contextual Info: QL8X12A pASIC 1 FAMILY Very-High-Speed IK 3K Gate CMOS FPGA A pril 1993 pASIC HIGHLIGHTS Eg Very-High-Speed, Flexible FPGA Architecture - ViaLink metal-tometal, low-resistance antifuse (<50 ohm) interconnect technology allows data path performance over 125 MHz with logic cell delays of under 2.5 ns.

Contextual Info: bSE » • TOGBDBO DDGDlb? 47T « f l U I C QL8X12A pASIC 1 FAMILY Very-High-Speed IK 3K Gate CMOS FPGA April 1993 pASIC HIGHLIGHTS .3000 total available gates Q Very-High-Speed, Flexible FPGA Arcliitecture - ViaLink metal-tometal, low-resistance antifuse (<50 ohm) interconnect technology allows

QL8X12A

Abstract: pl68c 96
Contextual Info: QL8X12A pASIC 1 FAMILY Very-High-Speed IK 3K Gate CMOS FPGA April 1993 pASIC HIGHLIGHTS RSI Very-High-Speed, Flexible FPGA Architecture - ViaLink metal-tometal, low-resistance antifuse (<50 ohm) interconnect technology allows data path performance over 125 MHz with logic cell delays of under 2.5 ns.

Contextual Info: Q L 8X 12B pASIC 1 Family Very-High-Speed CMOS FPGA Rev B pASIC HIGHLIGHTS Very High Speed - ViaLink" metal-to-metal programmable-via antifuse technology, allows counter speeds over 150 MHz and logic cell delays of under 2 ns. . 1,000 usable ASIC gates,

report on PLCC

Abstract: 40673 plcc 68 QL8X12A reliability report solar cell Amorphous 40673 equivalent ql8x12 144TQFP PACKAGE QL8X12B
Contextual Info: SUMMARY August 1997 The pASIC device is a highly reliable Field Programmable Gate Array. The addition of the ViaLink to a CMOS process does not measurably increase the failure rate of the pASIC devices above that of normal CMOS logic products. The following is the summary of the High

Signal Path Designer

Contextual Info: QAN9 Optimizing pASIC Architecture Designs DESIGNING FOR SPEED Many FPGAs require careful study of the device architecture. Beginner designers may find that such devices require tremendous effort to achieve the originally anticipated result. Often, expert designers are needed to meet the

QP-PL84G

Abstract: QL8X12B-2pl68c TQFP 100 pin Socket CQFJ 84 socket 68 pin plcc socket view bottom PL84 QL12X16B QL8X12B pASIC 1 Family QL12x16B "pin compatible"
Contextual Info: pASIC Designer Programmer User's Guide May 1997 Copyright Information Copyright 1991-1997 QuickLogic Corporation. All rights reserved. The information contained in this manual and the accompanying software program are protected by copyright; all rights are reserved by QuickLogic Corporation.

pj 989

Abstract: PASIC 380 145026 14093 38980 report on PLCC solar cell Amorphous 144TQFP PACKAGE 84 pin plcc ic base QL8X12B-2
Contextual Info: pASIC 1 FAMILY Reliability Report SUMMARY The pASIC device is a highly reliable Field Programmable Gate Array. The addition of the ViaLink to a CMOS process does not measurably increase the failure rate of the pASIC devices above that of normal CMOS logic products. The following is the summary of the High