QL3012R Search Results

pf144

Contextual Info: QL3012 / QL3012R 12,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density PRELIMINARY DATA March, 1998 2 … 12,000 usable PLD gates, 118 I/O pins 11,520 bit RAM Option High Performance and High Density -12,000 Usable PLD Gates with 118 I/Os

QL3012-1PF100C

Abstract: QL3012-1PQ144C 100-PIN 84-PIN PF144 QL3012
Contextual Info: QL3012 / QL3012R 12,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density PRELIMINARY DATA February, 1998 2 … 12,000 usable PLD gates, 118 I/O pins 11,520 bit Ram Option High Performance and High Density -12,000 Usable PLD Gates with 118 I/Os

Contextual Info: QL3012 / QL3 0 1 2 R 12,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density PRELIMINARY DATA . 12,000 usable PLD gates, 118 I/O pins 11,520 bit RAM Option E High Performance and High Density -12,000 Usable PLD Gates with 118 I/Os

intel 4040

Abstract: QL3004 transistor equivalent table 557 cmos 4040 datasheet general cross references QL5064 QL4009 QL4016 QL4058 QL5030
Contextual Info: EMBEDDED STANDARD PRODUCT A GENERATION AHEAD ! The Vialink Antifuse in 0.35µ µm CMOS QuickLogic Corporation 1277 Orleans Dr. Sunnyvale, CA 94089-1138 General Information: Applications Hotline FAX: EMAIL: WEB SITE: 408 990-4000 (408) 990-4100 (408) 990-4040

cpu Intel 4040

Abstract: intel 4040 3com 226 QAN19 Modulating Direct Digital Synthesizer in a QuickLogic FPGA QL3025 pASIC 1 Family 4040 cmos 4040 intel cmos 4040 datasheet
Contextual Info: LEADING THE REVOLUTION IN FPGAs The Vialink Antifuse in 0.35µm CMOS QuickLogic Corporation 1277 Orleans Dr. Sunnyvale, CA 94089-1138 General Information: Applications Hotline FAX: EMAIL: WEB SITE: 408 990-4000 (408) 990-4100 (408) 990-4040 info@quicklogic.com

100-PIN

Abstract: 84-PIN PF100 PF144 PL84 QL3012 QL3012-1PF100C QL3012-1PQ144C
Contextual Info: QL3012 12,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density April, 1999 4 pASIC 3 HIGHLIGHTS … 12,000 usable PLD gates, 118 I/O pins High Performance and High Density -12,000 Usable PLD Gates with 118 I/Os -16-bit counter speeds over 300 MHz, data path speeds over 400 MHz

Contextual Info: QL3012 12,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density April, 1999 pASIC 3 HIGHLIGHTS . 12,000 usable PLD gates, 1181/0 pins S High Performance and High Density -12,000 Usable PLD Gates with 118 I/Os -16-bit counter speeds over 300 MHz, data path speeds over 400 MHz