PUMA2S1000 Search Results

Contextual Info: mosaic / f a — ^ 3 2 K x 3 2 SRAM M O D U LE semiconductor, inc. PUMA2S1000-025/35/45 Issue4.1 : February 1996 Description The PUMA 2S1000 is a 1Mbit high speed static RAM organised as 32K x 32 in a 66 pin ceramic PGA package. Access times of 25ns, 35ns or

2S100

Contextual Info: PUMA 2S1000 moìaic PUMA 2S1000-020/025 Issue 1.2: April 1992 ADVANCE PRODUCT INFORMATION S e m ic o n d u c to r - Pin Definition 1,048,576 bit CMOS High Speed Static RAM 1 Features User Configurable as 8,16 or 32 bit wide Very Fast access times of 20/25 ns.

Contextual Info: 32K X 32 SRAM MODULE mosaic semiconductor, inc. PUMA 2S1000 - 020/025/35/45 11403 West Bernado Court, Suite 100, San Diego, CA 92127. Tel No: 619 674 2233, Fax No: (619) 674 2230 Issue 4.3 : N o vem b er 1998 Description 1,048,576 bit CMOS High Speed Static RAM

Contextual Info: 3 tnt PUMA 2S1000 molate PUMA 2S1000-35/45/55/70 Issue 3.2 : MAY 1992 ADVANCE PRODUCT INFORMATION S e m ic o n d u c to r C Pin Definition 1,048,576 bit CMOS High Speed Static RAM 1 Features Very Fast access times of 35/45/55/70 ns. Configurable as 32 / 1 6 / 8 bit wide output.

Contextual Info: ft?* «B PUMA 2S1000 molate PUMA 2S1000-020/025 Issue 1.2: April 1992 ADVANCE PRODUCT INFORMATION S e m ic o n d u c to r Inc. ' \ Pin Definition 1,048,576 bit CMOS High Speed Static RAM Features User Configurable as 8,16 or 32 bit wide Very Fast access times of 20/25 ns.

SRAM 6T

Abstract: MSM8128 "32K x 8" SRAM dil SRAM 35ns "32K x 8" SRAM PLCC 2035 puma 5 128k x 8 eeprom JLCC
Contextual Info: Part Numbering M S M 8512 SC X L MB - 10 1. 2. 3. 4. 1. 2. Speed 7. 6. 5. TECHNOLOGY 5. PINOUT ARRANGEMENT The memory technology is represented by a single character:- This field identifies the mechanical arrangement of the device pinout:- S D E U blank E

Contextual Info: PUMA 2S1000 molate PUMA 2S1000-85/10/12/15 issue 3.0 : August 1990 S e m ic o n d u c to r Pin Definition inc. 1,048,576 bit CMOS High Speed Static RAM Features User Configurable as 8,16 or 32 bit wide Fast access times of 85/100/120/150 ns Pin grid array gives 2:1 improvement over DIL