PULSE ENGINEERING DELAY LINES Search Results

Delay Lines

Abstract: pulse engineering delay lines
Contextual Info: DELAY UNES Engineering Guidelines Bandwidth x Rise time = 0.35 <t> For 10 Tap lines: Rise time = ^ total delay © Rise time = total delay For 5 Tap lines: NB: In the case of Active Delay lines the ’Rise Time’ value in these expressions is that of the internally buffered LC network. The value is determined from

MIL-D-83531

Abstract: MIL-D-83532 pulse engineering delay lines
Contextual Info: Company Profile Founded in 1970, Rhombus Industries Incorporated is a privately owned corporation and a leading designer and manufacturer of delay lines and low power pulse transformers. The headquarters for Rhombus Industries is located in Huntington Beach, California and includes research and development, complete assembly and manufacturing capabilities,

Contextual Info: Toll-Free: 888 892-0761 www.pca.com Manufacturers of Quality Magnetic Components DC - DC DELAY LINES LAN & TELECOM PoE MAGNETICS LOW POWER MAGNETICS Designed For Switcher/Controller Chipsets From Maxim & Power Integration SMPS Flyback, Buck, Boost, Coupled Inductor, Forward,

Contextual Info: 2bMM3fl2 O D O l l b b 17b Multiple Monolithic Programmable Delay Lines SERIES: MPDU 8 BITS Parallel S e r ia l IN, C 1 AE, £ IN, Features 16 3 2 L 3 C 4 AE? Q 5 • ■ ■ ■ ■ ■ ■ All-silicon delay line technology Multiple PDU’s (2 ,4 ,8 ) per package

5-1147

Abstract: 882s 3D7408 mpdu
Contextual Info: 2t>MM3ä2 □ OOllL.b 17b Multiple Monolithic Programmable Delay Lines SERIES: MPDU 8 BITS S erial Parallel Features Description The MPDU 8-Bit Silicon Delay Line product family consists of multiple 8-bit, user-programmable CMOS silicon integrated circuits, in a single package

pulse engineering

Abstract: 92112
Contextual Info: PULSE ENGINEERING INC fai. ^ ' DEI QQQDSBT b ~ - . r r ACTIVE AU TO INSERTABLE DIP DDM > • AUTOMATICALLY INSERTABLE PACKAGE • 14 PIN INDUSTRY STANDARD PINOUT • 5 EQUALLY SPACED TAPS • TTL/DTL COMPATIBLE • LEADING EDGE PRECISION t-V.'. • • . .

Pulse Engineering

Abstract: 92112 21789 30-PIN 14or
Contextual Info: PULSE ENGINEERING INC bì ^ ' . ACTIVE • DE J 745ññt14 GODOSBT b ' . . . AUTO INSERTABLE DIP DDM y • AUTOMATICALLY INSERTABLE PACKAGE • 14 PIN INDUSTRY STANDARD PINOUT • 5 EQUALLY SPACED TAPS • TTL/DTL COMPATIBLE • LEADING EDGE PRECISION t-\V.

Logic Buffered

Abstract: Delay Lines APP1_LOG A Simple Rise and Fall Time Waveform Control schematic of TTL OR Gates Delay Modules "Delay Modules" MIL-D-83532 for the construction of cmos logic gates
Contextual Info: Logic Buffered Delay Modules General: To avoid the difficulties associated with interfacing passive delay lines with digital integrated circuits, active delay lines have been developed to provide design flexibility and circuit simplification. Logic buffered input and outputs prevent the

Contextual Info: Digitally Programmable Delay Lines series : PDU-2600 DIP PDU-2600S |(SMD) 'a m v j U'9h Accuracy1 ,See App|icati0n No|esCompensated 1&2 f,e(luency Test Conditions (for F, • Input pulse-width: > 150% of max. delay. ■ Input pulse spacing: > 3 times of max. delay.

Contextual Info: Logic Buffered Delay Modules G eneral: To avoid the difficulties associated with interfacing p assive delay lines with digital integrated circuits, active delay lines have been developed to provide design flexibility and circuit simplification. Logic buffered input and outputs prevent the

Contextual Info: Timing Definition For Programmable Delay Lines PDU’s Typical Set-Up Specifications f DO (ns) M inim um Input Pulso-W idth (ns) ‘ A bsolute •Suggested R ecom m ended M inim um Input Period (ns) 6 5.5 10% of T dt 2 X PW IN 9 9 8% of T dt 8% o l T dt

Contextual Info: Timing Definition For Programmable Delay Lines PDU’s Typical Set-Up Specifications Minimum Input Pulse-Width (ns) “Suggested Recommended Minimum Input Period (ns) 10% o f T dt 25% o f T dt G reater than T dt 2 X PW |N 8% o f T dt 8% o f T dt 2 0% of T dt

PDU-2600-1

Abstract: PDU-2600-2 PDU-2600-3 PDU-2600-4 PDU-2600-5 PDU-2600-6 PDU-2600-7
Contextual Info: Digitally Programmable Delay Lines s e r ie s : PDU-2600 DIP PDU-2600S (SMDI delay devices^me. Accuracy1 Compensated1 1Frequency $eeApp|jcation No,es, &2 H '9 h Test Conditions (for Ft , F, = Logic <•) • Input pulse-width: > 150% of max. delay. ■ Input pulsa spacing:

SGRAM

Abstract: ddr SGRAM 1993 synchronous dram jedec dram ddr 1997
Contextual Info: Memory Application Team Tel: 82-331-209-5371 Fax: 82-2-760-7990 GRAPHIC MEMORY APPLICATION NOTE How to implement DDR SGRAM in Graphic System 1 General concept of DDR SGRAM DDR SGRAM stands for “Double Data Rate Synchronous GRAM”. The term “double data rate” can

Digital TV transmitter receivers block diagram

Abstract: CS6158A CS6158-IL1 S553-0013-07 CS6158A-IL1 CS6158A-IP1 CS6158-IP1 pe-65761 pulse engineering pe
Contextual Info: Semiconductor Corporation T1/E1 Line Interface Features General Description • Provides Analog Transmission Line Interface forT1 and E1 Applications The CS6158 and CS6158A combine the complete ana­ log transmit and receive line interface for T1 or E1 applications in a low power, 28-pin device operating

nytronics delay

Abstract: pulse engineering delay lines MS3400DS44-52S L/C dt14cbxxx hy5002 DDU-222-XXX y1-05xxx 1405-0XXX L-52-XXX DL8100
Contextual Info: DELAY U N ES Interchangeability guide Newport Equivalent Series BAL 0204-XXX-XXX 0408-A X 0805-0XXX 0905-0XXX 1403-0XXX 1405-0XXX 1607-0XXX 381405XX 3814100XXX Newport Data Delay Devices 21A 11A 80A 70A 34A 42A 60A 31A 50A DDU-8-XXX MDU-3-XXX 613X/4X 63XX

DEI1016

Abstract: DEI1016A DEI 1016 CLCC footprint DEI1016-QMS DEI1016-PMS 3RD Rail Engineering
Contextual Info: Device Engineering Incorporated 385 East Alamo Drive Chandler, AZ 85225 Phone: 480 303-0822 Fax: (480) 303-0824 E-mail: info@deiaz.com DEI1016/DEI1016A/DEI1016B ARINC 429 Transceiver Family Features • • • • • • • • • • Two Receivers and One Transmitter

ISO-9002

Contextual Info: PCA and Its Products High Tech Design and Quality Workmanship PCA Electronics, Inc. began as a supplier of Pulse Transformers and Delay Lines. We were one of the original designers and manufacturers of 10Base-T Filters in the early 1990’s, as well as supplying 10/100Base-X and

Nokia 3210

Abstract: nokia c5-03 str z 4267 G4ad7 4-20 mA converter modbus rs485 ascii protocols G4D32RS G4ODC5 nokia display c5-03 CRC16
Contextual Info: MISTIC PROTOCOL USER’S GUIDE Form 270-100823 — August, 2010 43044 Business Park Drive, Temecula, CA 92590-3614 Phone: 800-321-OPTO 6786 or 951-695-3000 Fax: 800-832-OPTO (6786) or 951-695-2712 www.opto22.com Product Support Services: 800-TEK-OPTO (835-6786) or 951-695-3080

T2 WICKMANN FUSE

Abstract: t1.403 National Standard for Telecommunications ARRESTOR triac 131-6 raychem stress control tube schematic design for surge protector and electric Federal fuse switch transmission line transformers TVS-SM05 AN34
Contextual Info: AN34 Application Note Secondary Line Protection for T1 and E1 Line Cards Roger Taylor The lower cost of high speed digital T1 and E1 trunk lines has resulted in the increasing deployment of this technology in place of traditional analog lines. In the past, T1/E1 trunks were used

61Z14

Abstract: hy-5003 HY-5030-XXXR P107X HY 1505 pt36C Kappa Networks PS14A HY-5003-XXXR Polara Engineering
Contextual Info: ^ 4 3 -Û Z • b5T3mT ooQDiaa ise ■ . NEWPORT COI1PONENTS LTD nclb .nr- ri DELAY U N ES 4ÛE D Interchangeability guide Newport Equivalent Series BAL 0204-XXX-XXX 0408-A X 0805-0XXX 0905-0XXX 1403-0XXX 1405-0XXX 1607-0XXX 381405XX 3814100XXX Newport

Contextual Info: tm mm âm ^ m mm Semiconductor Corporation T1/E1 Line Interface Features General Description • Provides Analog Transmission Line Interface for T1 and E1 Applications The CS6158 and CS6158A combine the complete ana­ log transmit and receive line interface for T1 or E1

PIC18 example C18 codes

Abstract: PIC18 MSSP MASTER, SLAVE SPI ASSEMBLY SOURCE CODE PIC18f8722 example codes pulse PIC18 example codes SPI master PIC18 example codes i2c PIC18 example codes spi PIC18f8722 PWM sample code PIC18F8XXX PIC18 example C18 codes two device spi PIC18 example 18 C codes
Contextual Info: PIC18F6627/6722/8627/8722 PIC18F6627/6722/8627/8722 Rev. A1 Silicon Errata The PIC18F6627/6722/8627/8722 parts you have received conform functionally to the Device Data Sheet DS39646B , except for the anomalies described below. Any Data Sheet Clarification issues related to

Engineering Bulletins

Abstract: Neuron 3150 Neuron Chip 3150 Neuron LON TC55257CFL-70L MOTOROLA Neuron Chip Neuron A 3150 ic TC55257CFL TDSR 3150 l
Contextual Info: @ Neuron 3150® Chip External Memory Interface May 1995 L ON W ORKS ® Engineering Bulletin Introduction The Neuron 3150 Chip provides an external memory bus to permit expansion of memory up to 58K bytes beyond the 512 bytes of EEPROM and 2K bytes of RAM