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Catalog Datasheet	Type	Document Tags	PDF
52HL Abstract: ZD 103 ma 1M x 16 SRAM lfu 3sc w1A 74 IDT71T75602 IDT71T75802 Contextual Info: 512Kx36,1M x18 2.5V Synchronous ZBT SRAMs 2.5V I/O, Burst Counter Pipelined Outputs Features ♦ 512K x 36,1M x 18 memory configurations ♦ Supports high performance system speed - 200 MHz 3 2 ns Clock-to-Data Access ♦ ZBT™ Feature - No dead cycles between write and read	OCR Scan	512kx36 1mx18 idt71t75602 idt71t75802 +8119bga 225mhz 200mhz 52hl zd 103 ma 1m x 16 sram lfu 3sc w1a 74	PDF
JEDEC SPD No.21 Abstract: RA11b 227A capacitor ra5b TSOP 66 Package TNETD jesd 21c PC266 64mx8 SSTV16857 Contextual Info: JEDEC Standard No. 21–C Page 4.20.4–1 4.20.4– 184 PIN, PC1600/2100 DDR SDRAM REGISTERED DIMM DESIGN SPECIFICATION PC1600/2100 DDR SDRAM Registered DIMM Design Specification Revision 1.2 Release 11a Revision 1.2 JEDEC Standard No. 21–C Page 4.20.4–2	Original	pc1600/2100 jedec spd no.21 ra11b 227a capacitor +7ra5b tsop 66 package tnetd jesd 21c pc266 64mx8 sstv16857	PDF
CQ823 Contextual Info: 4ÛE5771 0G2bm2 bhS CMOS SyncFlFO 8192X9 FEATURES: • • • • • • • • • • • • 8192 x 9-bit organization Pin/function compatible with IDT72421/722x1 family 15 ns read/write cycle time Read and write clocks can be independent Dual-Ported zero fall-through time architecture	OCR Scan	e5771 idt72251 8192x9 idt72421/722x1 +432-pin publication95 registrationms-016 cq823	PDF

Catalog Datasheet

Type

Document Tags

PDF

52HL

Abstract: ZD 103 ma 1M x 16 SRAM lfu 3sc w1A 74 IDT71T75602 IDT71T75802
Contextual Info: 512Kx36,1M x18 2.5V Synchronous ZBT SRAMs 2.5V I/O, Burst Counter Pipelined Outputs Features ♦ 512K x 36,1M x 18 memory configurations ♦ Supports high performance system speed - 200 MHz 3 2 ns Clock-to-Data Access ♦ ZBT™ Feature - No dead cycles between write and read

OCR Scan

512kx36 1mx18 idt71t75602 idt71t75802 +8

PDF

JEDEC SPD No.21

Abstract: RA11b 227A capacitor ra5b TSOP 66 Package TNETD jesd 21c PC266 64mx8 SSTV16857
Contextual Info: JEDEC Standard No. 21–C Page 4.20.4–1 4.20.4– 184 PIN, PC1600/2100 DDR SDRAM REGISTERED DIMM DESIGN SPECIFICATION PC1600/2100 DDR SDRAM Registered DIMM Design Specification Revision 1.2 Release 11a Revision 1.2 JEDEC Standard No. 21–C Page 4.20.4–2

Original

pc1600/2100 jedec spd no.21 ra11b 227a capacitor +7

PDF

CQ823

Contextual Info: 4ÛE5771 0G2bm2 bhS CMOS SyncFlFO 8192X9 FEATURES: • • • • • • • • • • • • 8192 x 9-bit organization Pin/function compatible with IDT72421/722x1 family 15 ns read/write cycle time Read and write clocks can be independent Dual-Ported zero fall-through time architecture

OCR Scan

e5771 idt72251 8192x9 idt72421/722x1 +4

PDF