PSET 132 Search Results

PSET 132

Contextual Info: ECO-PACTM 2 Thyristor Module PSET 132/08-18 ITAVM VRRM = 132 A = 600-1800V Preliminary Data Sheet VRSM VDSM V 900 1300 1500 1700 1900 VRRM VDRM (V) 800 1200 1400 1600 1800 Type ACE-1 PSET 132/08 PSET 132/12 PSET 132/14 PSET 132/16 PSET 132/18 E-3 K-12 SVX-18

1555nm

Contextual Info: FSAN High Power Triplexer 1325-00003 Features • Low Cost 1310nm FP Design, 1490nm Digital Receiver, and 1555nm Analog Receiver • High Isolation • Multiple TIA Version for 155, 622, 1250 Mbps Applications • 1 GHz Video Reciever Bandwidth • Compliant to FSAN Class B ITU-T G.983.3 Specification

30-1847-GCCAS-01

Abstract: ADN2843 ADN2843CHIPSET ADN2843CHIPSET-B ADN2844 ADN2845 ADN2850 ADN2860 ADN2943 STM-64
Contextual Info: a 10.709 Gbps Laser Diode Driver Chipset ADN2843 FEATURES Data Rates from 9.952 Gbps to 10.709 Gbps Typical Rise/Fall Time 25 ps/23 ps Bias Current Range 3 mA to 80 mA Modulation Current Range 5 mA to 80 mA Monitor Photodiode Current 50 ␮A to 1200 ␮A Closed-Loop Control of Both Average Optical Power

30-1847-GCCAS-01

Abstract: ADN2843 ADN2843CHIPSET ADN2843CHIPSET-B ADN2844 ADN2845 ADN2850 ADN2860 ADN2943 STM-64
Contextual Info: a 10.709 Gbps Laser Diode Driver Chipset ADN2843 FEATURES Data Rates from 9.952 Gbps to 10.709 Gbps Typical Rise/Fall Time 25 ps/23 ps Bias Current Range 3 mA to 80 mA Modulation Current Range 5 mA to 80 mA Monitor Photodiode Current 50 ␮A to 1200 ␮A Closed-Loop Control of Both Average Optical Power

10667G

Abstract: ADN2843CHIPSET
Contextual Info: a 10.709Gb/s LASER DIODE DRIVER Chipset ADN2843 Preliminary Technical Data FEATURES Data Rates from 50Mb/s to 10.709Gb/s Typical rise/fall time 25/23 ps Bias Current range 3mA to 80 mA Modulation Current range 5mA to 80 mA µA to 1100µ µA Monitor Photo Diode current 50µ

TAG 206-100

Abstract: S5U1C62000A Manual 60N01 IEEE-695 62XXX IEEE695 com file ICE62
Contextual Info: MF1121-03a CMOS 4-BIT SINGLE CHIP MICROCOMPUTER S5U1C62000A Manual S1C60/62 Family Assembler Package NOTICE No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any

7313 28 pin

Abstract: 912 cristal Fuse FF8 ICE6200 sec LCD display 0838 seiko SMC62 xy r01a 03a a03 capasitor 104 epson gt
Contextual Info: MF364-02 CMOS 4-BIT SINGLE CHIP MICROCOMPUTER E0C6281 DEVELOPMENT TOOL MANUAL NOTICE No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice.

hp 2730

Abstract: xy r01a OPT0103 hp 2730 HP2730 hp 2418 printer logic card diagram TAB 429H MF385-02 IV-70 NEC 9801 IV-68
Contextual Info: MF385-02 CMOS 4-BIT SINGLE CHIP MICROCOMPUTER E0C6266 DEVELOPMENT TOOL MANUAL NOTICE 1. The information in this manual is subject to change without notice. 2. This manual has been prepared with great care. However, if you find an error, are in doubt about something, or have a comment or opinion, please contact

CS460

Abstract: cmos cross manual xy r01a r01f C2xx NEC 2415 W03A PC-9800 6200A 4 digits 7-segment led display
Contextual Info: MF599-06 CMOS 4-BIT SINGLE CHIP MICROCOMPUTER S1C62 Family Development Tool Reference Manual NOTICE No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any

40B5

Abstract: 42B2 RT54SX-S 49-pin
Contextual Info: v3.2 eX Automotive Family FPGAs u e Specifications • • • • • 3,000 to 12,000 Available System Gates Maximum 512 Flip-Flops Using CC Macros 0.22 µm CMOS Process Technology Up to 132 User-Programmable I/O Pins • • • • Features • •

Contextual Info: v3.0 eX Automotive Family FPGAs FuseLock Specifications • • • • • 3,000 to 12,000 Available System Gates Maximum 512 Flip-Flops Using CC Macros 0.22µm CMOS Process Technology Up to 132 User-Programmable I/O Pins • • • • Features • •

Contextual Info: v3.1 eX Automotive Family FPGAs FuseLock Specifications • • • • • 3,000 to 12,000 Available System Gates Maximum 512 Flip-Flops Using CC Macros 0.22µm CMOS Process Technology Up to 132 User-Programmable I/O Pins • • • • Features • •

Contextual Info: v3.0 eX Automotive Family FPGAs FuseLock Specifications • • • • • 3,000 to 12,000 Available System Gates Maximum 512 Flip-Flops Using CC Macros 0.22µm CMOS Process Technology Up to 132 User-Programmable I/O Pins • • • • Features • •

MF652-07

Abstract: e81h MF652 E86H epson c244 F42H HX 030 IC HP V5 Q13MC146 SRM2064 60N01
Contextual Info: MF652-07 CMOS 4-BIT SINGLE CHIP MICROCOMPUTER S1C62440/624A0/624C0/62480 Technical Manual S1C62440/624A0/624C0/62480 Technical Hardware S1C62440/624A0/624C0/62480 Technical Software NOTICE No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko

Contextual Info: Revision 5 ex Automotive Family FPGAs Specifications • 3,000 to 12,000 Available System Gates • Maximum 512 Flip-Flops Using CC Macros • 0.22 m CMOS Process Technology • Up to 132 User-Programmable I/O Pins Features • Live on Power-Up • No Power-Up/Down Sequence Required for Supply

STK 795 820 english

Abstract: sine wave inverter circuit diagram pa56c LADR2 026E3 uPD78366A 00116h 0348a stk 490 110 uPD78361A
Contextual Info: To our customers, Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid

EX256-TQ100

Contextual Info: Revision 10 eX Family FPGAs Leading Edge Performance • 240 MHz System Performance • 350 MHz Internal Performance • 3.9 ns Clock-to-Out Pad-to-Pad Specifications • 3,000 to 12,000 Available System Gates • Maximum 512 Flip-Flops (Using CC Macros)

UA 796

Abstract: 40B5 42B2 RT54SX-S TQFP-64 PACKAGE thermal resistance bst web guiding uA796 UA 795
Contextual Info: Revision 9 eX Family FPGAs FuseLock Leading Edge Performance • 240 MHz System Performance • 350 MHz Internal Performance • 3.9 ns Clock-to-Out Pad-to-Pad Specifications • 3,000 to 12,000 Available System Gates • Maximum 512 Flip-Flops (Using CC Macros)

SAW 433.92

Abstract: saw 433,92 "SAW 315" MHZ PCB u9280 SAW 111 B3942 j330 SAW315 pcb antenna 13.56Mhz M44C892
Contextual Info: Application Note RKE Design Kit U2741B, U3741BM 11.98 1 Application Note RKE Design Kit (U2741B, U3741BM) Table of Contents 1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

433 315 MHz RF Transmitter

Abstract: RF transmitter and receiver 433.9 433 mhz UHF RECEIVER, pcb layout and Schematic 433 mhz rf RECEIVER pcb layout RF transmitter and receiver 433.92 "SAW 315" MHZ PCB Telefunken remote control transmitter and receiver circuit transmitter 433.92 MHz 5v ask datasheet vishay resistor 0603 1% 0.1W
Contextual Info: Application Note RKE Design Kit U2741B, U3741BM Table of Contents 1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2. Hardware Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ADU01

Abstract: Intel P55 Chipset D31CD
Contextual Info: — ^ C Y M 7 4 B P 5 4 CYM 74P54/55 ^ l r t î m n r n P R E L IM IN A R Y . n wm W U ir K fc b b C Y M 7 4 S P 5 4 /5 5 — Intel 82430NX Chipset Level II Cache Module Family Feat ures • Pi n- compat i bl e secondary cache mo d ul e family • As yn ch r o no u s CYM7 4BP5 4 , sync h r o no us pipelined

Contextual Info: INTEL 440LX AGPSET: 82443LX PCI A.G.P. CONTROLLER PAC Supports the Pentium I I Processor at a Bus Frequency of 66 MHz — Supports 32-Bit Addressing — Optimized In-Order and Request Queue — Full Symmetric Multi-Processor (SMP) Protocol for Up to Two

40B5

Abstract: 42B2 RT54SX-S TQ100
Contextual Info: v4.1 eX Family FPGAs FuseLock Leading Edge Performance • • • • • 240 MHz System Performance 350 MHz Internal Performance 3.9 ns Clock-to-Out Pad-to-Pad • • • Specifications • • • • • 3,000 to 12,000 Available System Gates Maximum 512 Flip-Flops (Using CC Macros)

TU 55x

Abstract: NDM1-63 UEI 20 SP BA 9513
Contextual Info: CYM74B550 CYM 7 4 P 5 5 0 A C Y M 7 4 S 5 5 0 , CY M 7 4 S 5 5 1 OPTi Viper Chip Set Level II Cache Module Family vo lt S R A M s and 3.3 volt level translators. T hese m odules offer 3-2 -2-2 p e rfo rm an ce at GPU bus speeds up to 6 6 MHz. Features • Pi n- co mp a ti b le s e c on da ry c a c h e m o d u l e family