PROPAGATION Search Results
PROPAGATION Datasheets Context Search
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Contextual Info: TIEPAL10016P8-3C HIGH-PERFORMANCE ExCL mP A l CIRCUIT D 30 83. D EC E M B E R 1987 • ECL 100K PAL • High-Performance Operation Propagation Delay . . . 3 ns Max JT PACKAG E TOP VIEW I e e • • ■ - 2 2 0 mA Max • Replacement for 100K ECL Logic |
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tiepal10016p8-3c24-pin300-mii | |
PAL16L8 programming specifications
Abstract: TIBPAL16R4 TIBPAL16L8
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tibpal16l8-20mtibpal16r4tibpal16r6tibpal16r8+7 | |
TOSHIBA RECTIFIERContextual Info: Introduction Thank you very much for using TOSHIBA Semiconductor Devices. This volume is the latest 1994 Version o f the “ Recti fiers” Semiconductor Data Book. Recent years have seen the phenomenal propagation o f elec tronic equipment o f all kinds including information processing |
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toshiba rectifier | |
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Contextual Info: y UC1711 UC3711 UNITRODE Dual Ultra High-Speed FET Driver 15ns Propagation Delay 1.5A Source or Sink Output Drive Operation with 5V to 35V Supply High-Speed Schottky NPN Process 8-PIN MINIDIP Package ABSOLUTE MAXIMUM RATINGS note 1 Input Supply Voltage, V c c . 40V |
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uc1711uc371110oopfuc1709 | |
uc3825 design
Abstract: power supply design uc3825
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uc1825uc2825uc3825uc3825 design+1 | |
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Contextual Info: IN T E G R A T E D C IR C U IT S UC1823 UC2823 UC3823 U N IT R Q D E High Speed PWM Controller FEATURES Com patible w ith Voltage or Current-M ode Topologies Practical O peration @ Switching Frequencies to 1.0MHz 50ns Propagation Delay to Output High C urrent Totem Pole O utput 1,5A peak |
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uc1823uc2823uc3823-10nf | |
18n8Contextual Info: T IB P A D 18N8-6C HIGH-PERFORMANCE PROGRAMMABLE AD D RESS DECODER/NAND ARRAY D 3 0 8 6 , DECEMBER 1 9 8 7 Very High Speed Address Decoder Ideal for Use w ith High Speed Processors I/O Propagation Delay: 6 ns Max • Suitable for High Speed N A ND-NAND Logic |
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18n8-6c18n8 | |
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Contextual Info: 74AC11204 HEX INVERTER/CLOCK DRIVER D3427, O C TO B ER 1989 DW OR N PACKAGE Low-Skew Propagation Delay Specifications for Clock Driver Applications TOP VIEW 1Y[ 1 2Y [ 2 3Y [ 3 Flow-Through Architecture Optimizes PCB Layout * * * Package Options Include Plastic “Small |
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74ac11204d3427500-ma300-mil | |
up down counter truth tableContextual Info: TOSHIBA TC74AC169 4-bit Binary Up/Down Counter Features: • High Speed: fmax = ?MHz typ. at V cc = 5V • Low Power Dissipation: lcc = 8nA (max.) at Ta = 25°C • High Noise Immunity: VN,H= V ML= 28% V cc (min.) • Symmetrical Output Impedance: • Balanced Propagation Delays: tpLH = W |
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tc74ac169up down counter truth table | |
2D 1002 integrated circuitContextual Info: SN54173, SN54LS173A, SN74173, SN74LS173A 4-BIT D-TYPE REGISTERS WITH 3-STATE OUTPUTS SDLS067A – OCTOBER 1976 – REVISED JUNE 1999 D D D TYPE TYPICAL PROPAGATION DELAY TIME MAXIMUM CLOCK FREQUENCY ’173 23 ns 35 MHz ’LS173A 18 ns 50 MHz description SN54173, SN54LS173A . . . J OR W PACKAGE |
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sn54173sn54ls173asn74173sn74ls173a+4 | |
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Contextual Info: QuickSwitch Products QS316233 High-Speed CMOS QS3162233 QuickSwitch 32:16 Mux/Demux & c lu c T O R , iN c . FEATURES/BENEFITS DESCRIPTION • Enhanced N channel FET with no inherent diode to Vcc • 5£2 bidirectional switches connect inputs to outputs • Zero propagation delay, zero ground bounce |
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qs316233qs316223332-bit16-bit | |
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Contextual Info: [ /Title CD74 HCU04 /Subject (High Speed CMOS Logic Hex Inverter CD74HCU04 Data sheet acquired from Harris Semiconductor SCHS127D High-Speed CMOS Logic Hex Inverter February 1998 - Revised May 2004 Features Description • Typical Propagation Delay: 6ns at VCC = 5V, |
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cd74hcu04schs127dhcu04-55oc+1 | |
30INT
Abstract: TTL LA 78141 la 78141 pinout "CMOS GATE ARRAY" fuji st zo 607
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ticpal22v10z-25cticpal22v10z-30isrps007cd3323+6 | |
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Contextual Info: f j j PER ICOM PI3B3861 3.3V, Hot Insertion, 10-Bit, 2-Port, BusSwitch Product Features Product Description • Near zero propagation delay |
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24-pinpi3b386110-bitps8167b | |
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B1434Contextual Info: QuickSwitch Products q s 32x r 384 High-Speed C M O S w , Inc 2 ° - Bit L o w Resistance Bus Switches FEATURES/BENEFITS DESCRIPTION • Enhanced N channel FET with no inherent diode to Vcc • 2.5Q bidirectional switches connect inputs to outputs • Zero propagation delay, zero ground |
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qs32xr384mdsl-00344-00b1434 | |
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Contextual Info: NB3N106K 3.3V Differential 1:6 Fanout Clock Driver with HCSL Outputs Description The NB3N106K is a differential 1:6 Clock fanout buffer with High−speed Current Steering Logic HCSL outputs optimized for ultra low propagation delay variation. The NB3N106K is designed |
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nb3n106knb3n106k/d | |
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Contextual Info: ISO7520C ISO7521C SLLSE39C – JUNE 2010 – REVISED DECEMBER 2011 www.ti.com Low-Power 5 KV rms Dual Digital Isolators Check for Samples: ISO7520C, ISO7521C FEATURES 1 • • • • • • • Highest Signaling Rate: 1 Mbps Propagation Delay Less Than 20 ns |
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iso7520ciso7521csllse39ciso75com/clocks | |
TSSOP20 FOOTPRINT
Abstract: SMD Transistor DN
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gtl2003an11127tssop20 footprintsmd transistor dn | |
HCF4050
Abstract: HCF405
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hcf4010jesd13bhcf4050hcf405 | |
LVX4066GContextual Info: MC74LVX4066 Quad Analog Switch/ Multiplexer/Demultiplexer High−Performance Silicon−Gate CMOS The MC74LVX4066 utilizes silicon−gate CMOS technology to achieve fast propagation delays, low ON resistances, and low OFF−channel leakage current. This bilateral switch/multiplexer/ |
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mc74lvx4066lvx4066mc14066hc4066a+2 | |
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Contextual Info: MC74VHC1G125 Noninverting 3-State Buffer Features • • • • • • • High Speed: tPD = 3.5 ns Typ at VCC = 5 V Low Power Dissipation: ICC = 1 mA (Max) at TA = 25°C Power Down Protection Provided on Inputs Balanced Propagation Delays Pin and Function Compatible with Other Standard Logic Families |
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mc74vhc1g125sc-88aot-353sc-70+1 | |
TS3011
Abstract: k540 TS301
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ts3011hbm/200ot23-5sc70-5+2 | |
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Contextual Info: 3V LVTTL-TO-DIFFERENTIAL LVPECL AND DIFFERENTIAL LVPECL-TO-LVTTL TRANSLATOR SY10EPT28L SY100EPT28L FINAL FEATURES • 3.3V ±10% power supply ■ Guaranteed AC parameters over temperature: fMAX > 275MHz LVTTL ■ < 2ns LVPECL-to-LVTTL propagation delay ■ < 600ps LVTTL-to-LVPECL propagation delay |
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275mhz600pssy10ept28lsy100ept28l+2 | |
elt25Contextual Info: DIFFERENTIAL ECL-to-TTL TRANSLATOR FEATURES • ■ ■ ■ ■ DESCRIPTION 2.6ns typical propagation delay Differential ECL inputs 24mA TTL outputs Flow-through pinouts Available in 8-pin SOIC package The SY100ELT25 is a differential ECL-to-TTL translator. Because ECL levels are used, a +5V, –5.2V |
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sy100elt25elt25 | |