PROGRAMMABLE LOGIC ARRAY FEATURES Search Results

DIN173

Abstract: application of programmable array logic 20L10 PLUS173
Contextual Info: Philips Semiconductors Programmable Logic Devices Product specification Programmable logic array 22 x 42 × 10 DESCRIPTION PLUS173–10 FEATURES The PLUS173–10 PLD is a high speed, combinatorial Programmable Logic Array. The Philips Semiconductors state-of-the-art

16l8 JEDEC fuse

Abstract: DIN153 Programmable Logic Array PLUS153-10N PLUS153 16L8 PLUS153-10A
Contextual Info: Philips Semiconductors Programmable Logic Devices Product specification Programmable logic array 18 x 42 × 10 DESCRIPTION PLUS153–10 FEATURES The PLUS153–10 PLD is a high speed, combinatorial Programmable Logic Array. The Philips Semiconductors state-of-the-art

RCT5 rn

Abstract: d-latch by using D flip-flop 7474 7474 counter circuit diagram I18N 8 bit barrel shifter
Contextual Info: Philips Components-Signetics Designing with Programmable Macro Logic Program m able Logic Devices INTRODUCTION TO PML DESIGN CONCEPTS Programmable Macro Logic, an extension of the Programmable Logic Array PLA concept combines a programming or fuse array with

ic D flip flop 7474

Abstract: IC 7474 truthtable philips for ic 7474 7474 D flip-flop circuit diagram PLHS502 7474 D flip-flop IC 7474 flipflop pin DIAGRAM OF IC 7474 INTERNAL DIAGRAM OF IC 7474 any boolean circuit using nand gates
Contextual Info: Philips Semiconductors Programmable Logic Devices Designing with programmable macro logic INTRODUCTION TO PROGRAMMABLE MACRO LOGIC DESIGN CONCEPTS Programmable Macro Logic PML , an extension of the Programmable Logic Array (PLA) concept combines a programming or

PLS161

Abstract: PLS161N
Contextual Info: PLS161 Signetics Field-Programmable Logic Array 12 X 48 X 8 Signetics Programmable Logic Product Specification Application Specific Products • Series 24 DESCRIPTION FEATURES The PLS161 is a bipolar, Field-Programmable Logic Array (FPLA). The device utilizes the standard AND/OR/lnvert ar­

XC2064

Abstract: XC2000 XC2018
Contextual Info:  XC2000 Logic Cell Array Family Product Specifications Features Description • Fully Field-Programmable: The Logic Cell Array LCA is a high density CMOS integrated circuit. Its user-programmable array architecture is made up of three types of configurable elements:

Contextual Info: DENSE-PAC Programmable Logic DPL22V10A MICROSYSTEMS DESCRIPTION: The Dense-Pac Programmable Logic Module DPL is a 48-pin Pin Grid Array (PGA) designed to support two "22V10" field programmable array logic, 22 input, 10 macrocell output devices (DPL22V10A), including decoupling capacitors, at a

Contextual Info: INTERNATIONAL CMOS TECHNOLOGY, INC. Preliminary Data TM PA7024 PEEL Array CMOS Programmable Electrically Erasable Logic Array Features User-Configurable High Density Logic Array — — — — Flexible Architecture Create multi-level l/O-buried logic circuits

Contextual Info: INTERNATIONAL CMOS TECHNOLOGY, INC. Preliminary Data TM PA7040 PEEL Array CMOS Programmable Electrically Erasable Logic Array Features Flexible Architecture User-Configurable High Density Logic Array — — — — Create multi-level l/O-buried logic circuits

PA7140J-20

Abstract: PA7140P-25 LCC14 PA7140 PA7140F-20 PA7140JN-20 PA7140P-20 "Programmable Electrically Erasable Logic Array"
Contextual Info: Commercial/ Industrial PA7140 PEELTM Array Features • ■ Programmable Electrically Erasable Logic Array Versatile Logic Array Architecture - 24 I/Os, 14 inputs, 60 registers/latches - Up to 72 logic cell output functions - PLA structure with true product-term sharing

"XOR Gate"

Abstract: karnaugh map 8 pin dip j k flipflop ic
Contextual Info: PAL22RX8A High Speed Programmable Array Logic Ordering Inform ation Features/ Benefits • Programmable flip-flops allow J-K, S-R, T or D-types for the most efficient use of product terms PAL22RX8A C NS STD PROGRAMMABLE ARRAY LOGIC • 8 Input/output macrocells for flexibility

22V10PLD

Abstract: 74ls74 timing setup hold PA7Q24
Contextual Info: PA7024 PEEL Array mimi SEMICONDUCTORS February 1993 Features General Description User-Configurable High Density Logic Array The PA7024 is a user-configurable high-density Programmable Electrically Erasable Logic PEEL Array for creating multi-level, l/O-buried, logic circuits. Designed

FLEX 9000 family

Contextual Info: FLEX 10K Embedded-Array Programmable Logic Device Family March 1995, ver. 1 Features Preliminary Information Advance Information Brief • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ High-density, embedded-array programmable logic device family

Contextual Info: Preliminary Information INC. TM PA7128 PEEL Array CMOS Programmable Electrically Erasable Logic Array Features Flexible Architecture User-Configurable High Density Logic Array — — — — — — Create multi-level l/O-buried logic circuits O ver 50 sum -of-products functions

Contextual Info: PA7140 INC. PA7140 PEEL Array Programmable Electrically Erasable Logic Array Features • Versatile Logic Array Architecture - ■ ■ 24 l/Os, 14 inputs, 60 registers/latches Up to 72 logic cell output functions PLA structure w ith true product-term sharing

Contextual Info: Military CMOS Programmable Gate Array Logic Cell Array M 2 0 6 4 /M 2 0 1 8 Conforms to MIL-STD-883, Class B* Ordering Information Benefits Features CMOS • Low power • TTL or CMOS Input threshold levels PROGRAMABLE • Programmable Logic unctions • Programmable I/O blocks

LCA-MEK01

Abstract: 2064 ram
Contextual Info: Military CMOS Programmable Gate Array Logic Cell Array M 2064/M 2018 Conforms to MIL-STD-883, Class B* Ordering Information Benefits Features CM OS • Low power • T T L or CM OS input threshold levels PROGRAM ABLE • Programmable Logic functions • Programmable I/O blocks

PML2552-50A

Abstract: EST 7502 C DIN552 est 7502
Contextual Info: Philips Semiconductors Programmable Logic Devices Product specification CMOS high density programmable macro logic FEATURES DESCRIPTION • Full connectivity The Philips Semiconductors PML family of PLDs provides "instant gate array" capabilities for general purpose logic

PAL10L8

Abstract: PAL14L4 pal16l2 PAL10L8 logic diagram PAL10L8A PAL12L6
Contextual Info: National Semiconductor Programmable Array Logic PAL 20-Pin Small PAL Family General Description The Small PAL logic array has between 10 and 16 comple­ mentary Input pairs and up to 8 combinatorial outputs gener­ ated by a single programmable AND-gate array with fixed

THX 201

Abstract: 26V12 PA7536 I326
Contextual Info: PA7536 PEEL Array Programmable Electrically Erasable Logic Array Versatile Logic Array Architecture - 12 I/Os, 14 inputs, 36 registers/latches - Up to 36 logic cell output functions - PLA structure with true product-term sharing - Logic functions and registers can be I/O-buried

pal macrocells

Contextual Info: MAPL244 44-Pin Multiple Array Programmable Logic General Description Features The MAPL244 is a medium density, electrically erasable CMOS EECMOS programmable logic device based on a proprietary National Semiconductor programmable logic ar­ ray architecture. The MAPL244 integrates paged Field Pro­

28U1

Abstract: 22V10
Contextual Info: DENSE-PAC MICROSYSTEMS Programmable Logic DPL22V10A D ESC R IP TIO N : The Dense-Pac Programmable Logic Module DPL ¡s a 48-p¡n Pin Grid Array (PGA) designed to support two "2 2 V 1 0 " field programmable array logic, 22 input, 10 macrocell output devices (D PL22V10A), including decoupling capacitors, at a

EK-025-8902

Contextual Info: H D G p GDK] / EPL204ED/EP EK-025-8902 CMOS ELECTRICALLY PROGRAMMABLE LOGIC • OUTLINE The EPL204 is a field programmable logic array manufactured by using CMOS EPROM processes. It is a programmable "and" fixed " o r " array w ith registered outputs in the 26P8

PAL10P8

Abstract: PAL10P8A
Contextual Info: « . Kl* «*, Programmable Array Logic Family XZZSSgSL*. / / / / /////////////////////////////////////MDVANCE INFORMATION Features/ Benefits • 25 ns maximum propagation delay Product Description • Programmable output polarity PART N UM BER PKG • Programmable replacement lor TTL logic