PROGRAMMABLE LOGIC ARRAY FEATURES Search Results

DIN173

Abstract: application of programmable array logic 20L10 PLUS173
Contextual Info: Philips Semiconductors Programmable Logic Devices Product specification Programmable logic array 22 x 42 × 10 DESCRIPTION PLUS173–10 FEATURES The PLUS173–10 PLD is a high speed, combinatorial Programmable Logic Array. The Philips Semiconductors state-of-the-art

16l8 JEDEC fuse

Abstract: DIN153 Programmable Logic Array PLUS153-10N PLUS153 16L8 PLUS153-10A
Contextual Info: Philips Semiconductors Programmable Logic Devices Product specification Programmable logic array 18 x 42 × 10 DESCRIPTION PLUS153–10 FEATURES The PLUS153–10 PLD is a high speed, combinatorial Programmable Logic Array. The Philips Semiconductors state-of-the-art

ic D flip flop 7474

Abstract: IC 7474 truthtable philips for ic 7474 7474 D flip-flop circuit diagram PLHS502 7474 D flip-flop IC 7474 flipflop pin DIAGRAM OF IC 7474 INTERNAL DIAGRAM OF IC 7474 any boolean circuit using nand gates
Contextual Info: Philips Semiconductors Programmable Logic Devices Designing with programmable macro logic INTRODUCTION TO PROGRAMMABLE MACRO LOGIC DESIGN CONCEPTS Programmable Macro Logic PML , an extension of the Programmable Logic Array (PLA) concept combines a programming or

PLS161

Abstract: PLS161N
Contextual Info: PLS161 Signetics Field-Programmable Logic Array 12 X 48 X 8 Signetics Programmable Logic Product Specification Application Specific Products • Series 24 DESCRIPTION FEATURES The PLS161 is a bipolar, Field-Programmable Logic Array (FPLA). The device utilizes the standard AND/OR/lnvert ar­

XC2064

Abstract: XC2000 XC2018
Contextual Info:  XC2000 Logic Cell Array Family Product Specifications Features Description • Fully Field-Programmable: The Logic Cell Array LCA is a high density CMOS integrated circuit. Its user-programmable array architecture is made up of three types of configurable elements:

Contextual Info: DENSE-PAC Programmable Logic DPL22V10A MICROSYSTEMS DESCRIPTION: The Dense-Pac Programmable Logic Module DPL is a 48-pin Pin Grid Array (PGA) designed to support two "22V10" field programmable array logic, 22 input, 10 macrocell output devices (DPL22V10A), including decoupling capacitors, at a

Contextual Info: INTERNATIONAL CMOS TECHNOLOGY, INC. Preliminary Data TM PA7024 PEEL Array CMOS Programmable Electrically Erasable Logic Array Features User-Configurable High Density Logic Array — — — — Flexible Architecture Create multi-level l/O-buried logic circuits

Contextual Info: INTERNATIONAL CMOS TECHNOLOGY, INC. Preliminary Data TM PA7040 PEEL Array CMOS Programmable Electrically Erasable Logic Array Features Flexible Architecture User-Configurable High Density Logic Array — — — — Create multi-level l/O-buried logic circuits

PA7140J-20

Abstract: PA7140P-25 LCC14 PA7140 PA7140F-20 PA7140JN-20 PA7140P-20 "Programmable Electrically Erasable Logic Array"
Contextual Info: Commercial/ Industrial PA7140 PEELTM Array Features • ■ Programmable Electrically Erasable Logic Array Versatile Logic Array Architecture - 24 I/Os, 14 inputs, 60 registers/latches - Up to 72 logic cell output functions - PLA structure with true product-term sharing

FLEX 9000 family

Contextual Info: FLEX 10K Embedded-Array Programmable Logic Device Family March 1995, ver. 1 Features Preliminary Information Advance Information Brief • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ High-density, embedded-array programmable logic device family

Contextual Info: Preliminary Information INC. TM PA7128 PEEL Array CMOS Programmable Electrically Erasable Logic Array Features Flexible Architecture User-Configurable High Density Logic Array — — — — — — Create multi-level l/O-buried logic circuits O ver 50 sum -of-products functions

Contextual Info: Preliminary Information INC. TM PA7140 PEEL Array CMOS Programmable Electrically Erasable Logic Array Features Flexible Architecture User-Configurable High Density Logic Array — — — — — — Create multi-level l/O-buried logic circuits Over 120 sum-of-products functions

Contextual Info: PA7140 INC. PA7140 PEEL Array Programmable Electrically Erasable Logic Array Features • Versatile Logic Array Architecture - ■ ■ 24 l/Os, 14 inputs, 60 registers/latches Up to 72 logic cell output functions PLA structure w ith true product-term sharing

LCA-MEK01

Abstract: 2064 ram
Contextual Info: Military CMOS Programmable Gate Array Logic Cell Array M 2064/M 2018 Conforms to MIL-STD-883, Class B* Ordering Information Benefits Features CM OS • Low power • T T L or CM OS input threshold levels PROGRAM ABLE • Programmable Logic functions • Programmable I/O blocks

EK-025-8902

Contextual Info: H D G p GDK] / EPL204ED/EP EK-025-8902 CMOS ELECTRICALLY PROGRAMMABLE LOGIC • OUTLINE The EPL204 is a field programmable logic array manufactured by using CMOS EPROM processes. It is a programmable "and" fixed " o r " array w ith registered outputs in the 26P8

Contextual Info: Commercial/ Industrial INC. TM PA7128 PEEL Array Programmable Electrically Erasable Logic Array Features • CMOS Electrically Erasable Technology - Reprogrammable in 28-pin DIP, SOIC, and PLCC packages I Versatile Logic Array Architecture - 12 l/Os, 14 inputs, 36 registers/latches

Contextual Info: Commercial/ Industrial INC. TM PA7140 PEEL Array Programmable Electrically Erasable Logic Array Features I CMOS Electrically Erasable Technology - Reprogrammable in 40-pin DIP and 44-pin PLCC packages I Versatile Logic Array Architecture - 24 l/Os, 14 inputs, 60 registers/latches

xc4300

Abstract: xc4310 XC4400 clb-1 XC4305 XC4000 XC4002A XC4004A 131C-3 XC4313
Contextual Info: XC4300 HardWire Array Family  Product Specification Features Description • Mask-programmed versions of Programmable Logic The XC4300 HardWire Array are mask-programmed versions of the XC4000 programmable devices. In volume applications where the design is stable, the programmable

C3415

Abstract: C3418 C3417 7C341-30 c341 transistor 84-PIN CY7C341 C3416 CY7C341-25HC 7C341-25
Contextual Info: 41 CY7C341 192-Macrocell MAX EPLD Features • • • • • • Programmable Interconnect Array 192 macrocells in 12 logic array blocks LABs Eight dedicated inputs, 64 bidirectional I/O pins 0.8-micron double-metal CMOS EPROM technology Programmable interconnect array

HA 12038

Contextual Info: XC2000 Logic Cell Array Family Product Specifications Features • Fully Field-Programmable: - I/O functions - Digital logic functions - Interconnections • General-purpose array architecture • Complete user control of design cycle • Compatible arrays with logic cell complexity equiva­

Contextual Info: fi XC2000 Logic Cell Array Family Product Specifications Features • Fully Field-Programmable: - I/O functions - Digital logic functions - Interconnections • General-purpose array architecture • Complete user control of design cycle • Compatible arrays with logic cell complexity equiva­

Contextual Info: KXILINX XC2000 Logic Cell Array Families Product Description Features • Fully Field-Programmable: - I/O functions - Digital logic functions - Interconnections • General-purpose array architecture • Complete user control of design cycle • Compatible arrays with logic cell complexity equiva­

TLO 81

Abstract: 16009A ICT Peel 26V12 PA7536 ma706
Contextual Info: Commercial/Industrial PA7536 PEEL Array Programmable Electrically Erasable Logic Array CMOS Electrically Erasable Technology - Reprogrammable in 28-pin DIP, SOIC and PLCC packages Versatile Logic Array Architecture - 12 I/Os, 14 inputs, 36 registers/latches

T flip flop CMOS IC

Abstract: blf 188
Contextual Info: FLEX10KE Embedded Programmable Logic Family May 1999» ver.2 Data Sheet $§ Features. Preliminary Information ^ Embedded programmable logic devices PLDs , providing System-on-a-Programmable-Chip integration in a single device Enhanced embedded array for implementing megafunctions