PRESET 10K DATASHEET Search Results

of preset 10k

Abstract: SN74S74 10k preset SN-7474
Contextual Info: SN5474, SN54LS74A, SN54S74 SN7474. SN74LS74A, SN74S74 DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR SDLS119 – DECEMBER 1983 – REVISED MARCH 1988 Copyright  1988, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date.

Contextual Info: SN5476, SN54LS76A SN7476, SN74LS76A DUAL J-K FLIP-FLOPS WITH PRESET AND CLEAR SDLS121 – DECEMBER 1983 – REVISED MARCH 1988 Copyright  1988, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments

Contextual Info: SN74F112 DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET SDFS048A – D2932, MARCH 1987 – REVISED OCTOBER 1993 • D OR N PACKAGE TOP VIEW Package Options Include Plastic Small-Outline Packages and Standard Plastic 300-mil DIPs 1CLK 1K

Contextual Info: IMPORTANT NOTICE Texas Instruments and its subsidiaries TI reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold

Contextual Info: IMPORTANT NOTICE Texas Instruments and its subsidiaries TI reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold

Contextual Info: 74ACT11074 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET SCAS498A – DECEMBER 1986 – REVISED APRIL 1996 D D D D D D, DB, OR N PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible Center-Pin VCC and GND Configurations to Minimize High-Speed Switching Noise

Contextual Info: SN54ALS112A, SN74ALS112A DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SDAS199A – APRIL 1982 – REVISED DECEMBER 1994 • SN54ALS112A . . . J PACKAGE SN74ALS112A . . . D OR N PACKAGE TOP VIEW Fully Buffered to Offer Maximum Isolation

A 2232

Contextual Info: SN54ALS109A, SN54AS109A, SN74ALS109A, SN74AS109A DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SDAS198B – APRIL 1982 – REVISED AUGUST 1995 • SN54ALS109A, SN54AS109A . . . J PACKAGE SN74ALS109A, SN74AS109A . . . D OR N PACKAGE TOP VIEW

Contextual Info: 74AC11074 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET SCAS499A – DECEMBER 1986 – REVISED APRIL 1996 D D D D D, N, OR PW PACKAGE TOP VIEW Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise EPIC  (Enhanced-Performance Implanted

Contextual Info: SN54ALS74A, SN54AS74A, SN74ALS74A, SN74AS74A DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET SDAS143C – APRIL 1982 – REVISED AUGUST 1995 • SN54ALS74A, SN54AS74A . . . J PACKAGE SN74ALS74A, SN74AS74A . . . D OR N PACKAGE TOP VIEW

Contextual Info: STA323W 2.1 channel high-efficiency digital audio system Datasheet - production data • Individual channel volume and EQ bypass  DDX POP free operation  Bass/treble tone control  Dual independent programmable limiters/compressors  AutoModes settings for:

epf10k10lc84-3

Abstract: 8 BIT microprocessor design with verilog hdl code EPF10K130EQC240-1 EPF10K50BC356-3 EPF10K100ARI240-3 epf10k50rc240-4 EPF10K50GC403-4 EPF10K10AFC256-2 EPF10K50VBI356-3 EPF10K130EFC484-3
Contextual Info: Includes FLEX 10KA FLEX 10K Embedded Programmable Logic Device Family March 2001, ver. 4.1 Features. Data Sheet • ■ ■ The industry’s first embedded programmable logic device PLD family, providing System-on-a-Programmable-Chip (SOPC) integration

ci 1458 texas

Contextual Info: SN54AHCT74, SN74AHCT74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET SCLS263M – DECEMBER 1995 – REVISED SEPTEMBER 2002 3 12 4 11 5 10 6 9 7 8 VCC 2CLR 2D 2CLK 2PRE 2Q 2Q 1D 1CLK 1PRE 1Q 1Q 14 1D 1 2 13 2CLR 3 12 2D 4 11 2CLK 5 10 2PRE

MC05J3

Abstract: LM272H LM388
Contextual Info: OBSOLETE LM27A www.ti.com SNOSAQ6D – MAY 2005 – REVISED APRIL 2013 LM27A ±3°C Accurate, 120°C-150°C Factory Preset Thermostat LM27 in Die Form Check for Samples: LM27A FEATURES DESCRIPTION • This datasheet applies to the LM27A, which is the die

Contextual Info: SN54HCT74, SN74HCT74 DUAL DĆTYPE POSITIVEĆEDGEĆTRIGGERED FLIPĆFLOPS WITH CLEAR AND PRESET SCLS169C – DECEMBER 1982 – REVISED DECEMBER 2002 D D D D D D D SN54HCT74 . . . J OR W PACKAGE SN74HCT74 . . . D, DB, N, NS, OR PW PACKAGE TOP VIEW Operating Voltage Range of 4.5 V to 5.5 V

PRESET 10K

Abstract: AHC74 marking 7850
Contextual Info: SN54AHC74, SN74AHC74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET SCLS255I – DECEMBER 1995 – REVISED SEPTEMBER 2002 D Operating Range 2-V to 5.5-V VCC Latch-Up Performance Exceeds 250 mA Per JESD 17 13 3 12 4 11 5 10 6 9 7 8 1D

Contextual Info: SN74LVC112A DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET SCAS289J – JANUARY 1993 – REVISED AUGUST 2002 D D D D D D D D, DB, DGV, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Inputs Accept Voltages to 5.5 V Max tpd of 4.8 ns at 3.3 V

Contextual Info: SN54ACT74, SN74ACT74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET SCAS520G – AUGUST 1995 – REVISED NOVEMBER 2002 D D D D SN54ACT74 . . . J OR W PACKAGE SN74ACT74 . . . D, DB, N, NS, OR PW PACKAGE TOP VIEW 4.5-V to 5.5-V VCC Operation

SN74LS74AN

Abstract: SN74LS74AP
Contextual Info: SN5474, SN54LS74A, SN54S74 SN7474. SN74LS74A, SN74S74 DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR SDLS119 – DECEMBER 1983 – REVISED MARCH 1988 Copyright  1988, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date.

SN74LS74AP

Abstract: SN74LS74AN
Contextual Info: SN5474, SN54LS74A, SN54S74 SN7474. SN74LS74A, SN74S74 DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR SDLS119 – DECEMBER 1983 – REVISED MARCH 1988 Copyright  1988, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date.

SN74ALS74ap

Contextual Info: SN54ALS74A, SN54AS74A, SN74ALS74A, SN74AS74A DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET SDAS143C – APRIL 1982 – REVISED AUGUST 1995 • SN54ALS74A, SN54AS74A . . . J PACKAGE SN74ALS74A, SN74AS74A . . . D OR N PACKAGE TOP VIEW

Contextual Info: SN54ALS109A, SN54AS109A, SN74ALS109A, SN74AS109A DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SDAS198B – APRIL 1982 – REVISED AUGUST 1995 • SN54ALS109A, SN54AS109A . . . J PACKAGE SN74ALS109A, SN74AS109A . . . D OR N PACKAGE TOP VIEW

preset variable resister 10k ohm

Abstract: 65asf transistor 8050d W83782D history of old speech control circuitry marking v6 zener diode 2N3904 W55FXX W83791D AH A01
Contextual Info: W83791D Winbond H/W Monitoring IC W83791D W83791D DataSheet Revision History Pages Dates 1 n.a. 2 n.a. 01/Jan 3 P.7 P.34 4 P.43/44 5 Version Version on Web n.a. All version before 0.5 are for internal use. 0.5 n.a. First publication. 01/Jan 0.51 n.a. 1 Revise SLOTOCC# pin description.

Contextual Info: SN54ALS112A, SN74ALS112A DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SDAS199A – APRIL 1982 – REVISED DECEMBER 1994 • SN54ALS112A . . . J PACKAGE SN74ALS112A . . . D OR N PACKAGE TOP VIEW Fully Buffered to Offer Maximum Isolation