PPD10 Search Results

Contextual Info: NEC pPD10500 262,144 x 1-Bit 10K BiCMOS ECL RAM NEC Electronics Inc. PRELIMINARY INFORMATION Description Pin Configuration pPD10500 is a very high-speed BiCMOS RAM with a 10K ECL interface. Its unique design uses blended CMOS and bipolar peripheral circuits and N-channel

Contextual Info: SEC PPD10500 262,144 x 1-Bit 10K BiCMOS ECL RAM NEC Electronics Inc. Description Pin Configuration T he /JPD10500 is a very high-speed BiCMOS RAM w ith a 10K ECL interface. Its unique design uses blended CM O S and bipolar peripheral circuits and N-channel

Nemic-Lambda power supply unit

Abstract: ppd10-24-1212 drawing RC-9002A pa5130 nemic lambda PPD10-48-1515 PPD10-12-1212 PPD10-5-1212 PPD10-5-1515 Nemic-Lambda power supply unit 5vdc PA513-01-01A
Contextual Info: PPD10-5 Specifications NEMIC-LAMBDA *:For delivery, contact to our sales office. PA512-01-01 MODEL PPD10-5-1212 PPD10-5-1515 ITEMS CH1 CH2 CH1 CH2 1 Nominal Output Voltage V +12 -12 +15 -15 2 Maximum Output Current A 0.35 0.35 0.30 0.30 3 Nominal Output Power

Contextual Info: TMS320VC5420 FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR SPRS080F − MARCH 1999 − REVISED OCTOBER 2008 D 200-MIPS Dual-Core DSP Consisting of Two D D D D D D D D D D D D D Independent Subsystems Each Core Has an Advanced Multibus Architecture With Three Separate 16-Bit

Contextual Info: TMS320VC5421 Fixed-Point Digital Signal Processor Data Manual Literature Number: SPRS098D December 1999 − Revised October 2008 PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments

TMDSDSK5416

Abstract: ci am 5766 IFR 840
Contextual Info: TMS320VC5420 FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR SPRS080E – MARCH 1999 – REVISED APRIL 2001 D 200-MIPS Dual-Core DSP Consisting of Two D D D D D D D D D D D D D Independent Subsystems Each Core Has an Advanced Multibus Architecture With Three Separate 16-Bit

PPD1R5-5-1515

Abstract: dc5v PPD1R5-24-1212 PPD3-24-1515 DC32 S PPD10-24-1212 ppd1r5-24-1515 PPD10-24-1515 12-1212 PPD3-5-1212
Contextual Info: PPD- series MMBDJIA DENSEI-LAMBDA Dual output DC-DC converter 1.5W ~ 10W Model name PPD 3-48-1212 1 Nominal output voltage — Nominal input voltage Name of series Output power • Features • Compact and dual output DC-DC converter Ultra-low profile: 8mm

TMS320C5420PGEA200

Abstract: TMS320VC5420 TMS320VC5420GGU200 TMS320VC5420PGE200
Contextual Info: TMS320VC5420 FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR SPRS080E – MARCH 1999 – REVISED APRIL 2001 D 200-MIPS Dual-Core DSP Consisting of Two D D D D D D D D D D D D D Independent Subsystems Each Core Has an Advanced Multibus Architecture With Three Separate 16-Bit

Contextual Info: TMS320VC5421 Fixed-Point Digital Signal Processor Data Manual Literature Number: SPRS098C December 1999 – Revised November 2001 PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments

Contextual Info: SM320VC5421-EP Fixed-Point Digital Signal Processor Data Manual Literature Number: SGUS047 July 2003 PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include

Contextual Info: TMS320VC5420 FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR SPRS080F − MARCH 1999 − REVISED OCTOBER 2008 D 200-MIPS Dual-Core DSP Consisting of Two D D D D D D D D D D D D D Independent Subsystems Each Core Has an Advanced Multibus Architecture With Three Separate 16-Bit

APPLE A6 CHIP

Abstract: cf325 W07 sot 23 C-492-5 SMD M05 sot23 C4977 cf406 p66 apple c5297 I342
Contextual Info: 8 6 7 PDF CSA CONTENTS IMG5 17" REV E 11/01/05 SYNC MASTER DATE PDF CSA CONTENTS TABLE_TABLEOFCONTENTS_HEAD 2 System Block Diagram FINO-DD 06/20/2005 TABLE_TABLEOFCONTENTS_ITEM 3 4 Power Block Diagram FINO-PC 06/20/2005 5 Table Items FINO-M23 08/26/2005 6

Contextual Info: TMS320VC5421 Fixed-Point Digital Signal Processor Data Manual Literature Number: SPRS098D December 1999 − Revised October 2008 PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments

Contextual Info: TMS320VC5421 Fixed-Point Digital Signal Processor Data Manual Literature Number: SPRS098D December 1999 − Revised October 2008 PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments

Contextual Info: TMS320VC5420 FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR SPRS080F − MARCH 1999 − REVISED OCTOBER 2008 D 200-MIPS Dual-Core DSP Consisting of Two D D D D D D D D D D D D D Independent Subsystems Each Core Has an Advanced Multibus Architecture With Three Separate 16-Bit

100484

Abstract: 100A484 100474 D-20 100476LL
Contextual Info: N E C ELECTRONICS INC blE D • ÆJJ W NEC Electronics Inc. L4E752S GG3534fl IGT « N E C E #iPD10500 262,144 X 1-Bit 10K BiCMOS ECL RAM T ' t t » -o 2 3 - ¿>5 - Description Pin Configuration The jiPD10500 is a very high-speed BiCMOS RAM with a 10K ECL interface. Its unique design uses blended

PPD1R5-12-1212

Abstract: ppd1r5-24-1212
Contextual Info: PP Series Low power isolatei DC-DC converters Low Profile For lower power 1,5W to 6W applications, Lambda’s low profile, low cost PP Series is an ideal solution. Available in Single Dual Outputs They have industry-standard pin-outs, a height of only 8mm and are available in single (5,12, & 15) and dual

TMS320C5420PGEA200

Abstract: TMS320VC5420 TMS320VC5420GGU200 TMS320VC5420PGE200
Contextual Info: TMS320VC5420 FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR SPRS080F − MARCH 1999 − REVISED OCTOBER 2008 D 200-MIPS Dual-Core DSP Consisting of Two D D D D D D D D D D D D D Independent Subsystems Each Core Has an Advanced Multibus Architecture With Three Separate 16-Bit

Contextual Info: NEC JUPD10500 262,144 X 1-Bit 10K BiCMOS ECL RAM NEC Electronics Inc. PRELIMINARY INFORMATION Description Pin Configuration pPD10500 is a very high-speed BiCMOS RAM with a 10K ECL interface. Its unique design uses blended CMOS and bipolar peripheral circuits and N-channel

Contextual Info: NEC JJPD100500 262,144 x 1-Bit 100K BiCMOS ECL RAM NEC Electronics Inc. PRELIMINARY INFORMATION Description Pin Configuration The/jPD100500 is a very high-speed BiCMOS RAM with full voltage and tem perature com pensation for a 100K ECL interface. Its unique design uses blended CMOS

TMS320VC5420

Abstract: TMS320VC5421 dlp dmd chip
Contextual Info: TMS320VC5421 Fixed-Point Digital Signal Processor Data Manual Literature Number: SPRS098D December 1999 − Revised October 2008 PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments

SM320VC5421-EP

Abstract: TMS320VC5420 TMS320VC5421
Contextual Info: SM320VC5421-EP Fixed-Point Digital Signal Processor Data Manual Literature Number: SGUS047 July 2003 PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include

Contextual Info: TMS320VC5420 FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR SPRS080F − MARCH 1999 − REVISED OCTOBER 2008 D 200-MIPS Dual-Core DSP Consisting of Two D D D D D D D D D D D D D Independent Subsystems Each Core Has an Advanced Multibus Architecture With Three Separate 16-Bit

Contextual Info: TMS320VC5420 FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR SPRS080F − MARCH 1999 − REVISED OCTOBER 2008 D 200-MIPS Dual-Core DSP Consisting of Two D D D D D D D D D D D D D Independent Subsystems Each Core Has an Advanced Multibus Architecture With Three Separate 16-Bit