POWER SUPPLY PS-02 DIAGRAM Search Results

Contextual Info: QUINT-PS/ 1AC/24DC/20 Primary-switched power supply with SFB technology, 1 AC, output current 20 A INTERFACE Data sheet 103129_en_04 1 PHOENIX CONTACT - 02/2010 Description QUINT POWER power supply units – Maximum system availability with SFB technology

F1DA104T

Abstract: computer mouse circuit diagram wireless microsoft computer mouse circuit diagram F3X1835-XX-GLD KVM SWITCH F1DA108T NeXT computer logitech optical mouse F1D082 logitech mouse diagram
Contextual Info: OmniView PRO2 Series KVM Switch User Manual F1DA104T F1DA108T F1DA116T PRO2 Series 13 TABLE OF CONTENTS Overview Feature Overview . . . . . . Equipment Requirements Operating Systems . . . . . Unit Display Diagrams . . Specifications . . . . . . . . .

Contextual Info: ICS9248-146 Integrated Circuit Systems, Inc. Frequency Generator & Integrated Buffers for Celeron & PII/III Block Diagram Pin Configuration VDDA * AGPSEL REF0 1 *(FS3)REF1 GND X1 X2 VDDPCI *(FS1)PCICLK_F *(FS2)PCICLK0 PCICLK1 PCICLK2 PCICLK3 PCICLK4 GND

SIS630S

Abstract: ICS9248-146 CPU-66 sis630
Contextual Info: ICS9248-146 Integrated Circuit Systems, Inc. Frequency Generator & Integrated Buffers for Celeron & PII/III Block Diagram Pin Configuration VDDA * AGPSEL REF0 1 *(FS3)REF1 GND X1 X2 VDDPCI *(FS1)PCICLK_F *(FS2)PCICLK0 PCICLK1 PCICLK2 PCICLK3 PCICLK4 GND

ICS9250-50

Abstract: 815B SEL24
Contextual Info: ICS9250-50 Integrated Circuit Systems, Inc. Frequency Generator & Integrated Buffers for PIII & Tualatin Block Diagram 48MHz 24_48MHz /2 XTAL OSC PLL1 Spread Spectrum FS 4:0 PD# Vtt_PWRGD SEL24_48# SDATA SCLK 0594A—07/08/02 REF0 CPU DIVDER 2 CPUCLK (1:0)

Contextual Info: * SYNERGY SEMICONDUCTOR FEATURES 50ps output-to-output skew Synchronous enable/disable Master Reset for synchronization Internal 75KQ input pull-down resistors ESD protection of 2000V PIN CONFIGURATION/BLOCK DIAGRAM [7 >1 ' +2 R < VCC |~3~ QD 16 V cc 15 EN

Contextual Info: ICS9248-195 Integrated Circuit Systems, Inc. Frequency Generator & Integrated Buffers for PENTIUM II/IIITM & K6 Block Diagram 48MHz 24_48MHz /2 XTAL OSC PLL1 Spread Spectrum 2 CPU DIVDER Stop Vtt_PWRGD/PD# PCI_STOP# CPU_STOP# CLK_STOP# 0375A—11/06/02 CPUCLK 2:0

Contextual Info: ICS94227 Integrated Circuit Systems, Inc. Programmable Frequency Generator for Celeron & PII/III Block Diagram PLL2 48MHz 24_48MHz /2 X1 X2 XTAL OSC PLL1 Spread Spectrum 2 CPU DIVDER Stop 2 CPUCLK 1:0 CPUCLK2/F Stop/F FS (4:0) PD# CPU_STOP# SDATA SCLK

94227AF

Abstract: ICS 94227 ics94227
Contextual Info: ICS94227 Integrated Circuit Systems, Inc. Programmable Frequency Generator for Celeron & PII/III Block Diagram PLL2 48MHz 24_48MHz /2 X1 X2 XTAL OSC PLL1 Spread Spectrum 2 CPU DIVDER Stop 2 CPUCLK 1:0 CPUCLK2/F Stop/F FS (4:0) PD# CPU_STOP# SDATA SCLK

CL1105

Abstract: PL02IN
Contextual Info: SILICON MMIC UPCONVERTER WITH AGC + IQ MODULATOR FEATURES_ INTERNAL BLOCK DIAGRAM • WIDE SUPPLY VOLTAGE RANGE: 2.7 to 5.5 V • OUTPUT FREQUENCY RANGE: 1.8 to 2.0 GHz • INTERNAL LPF TO REJECT LO & SPURIOUS LEAKAGE • PORTS FOR EXTERNAL IF FILTER

FS12

Abstract: ICS94252
Contextual Info: ICS94252 Integrated Circuit Systems, Inc. Programmable System Clock Chip for PIII Processor Block Diagram 48MHz XTAL OSC REF0 IOAPIC SDATA SCLK PLL1 Spread Spectrum CPU DIVDER Control SDRAM DIVDER PD# PCI_STOP# CPU_STOP# MODE 0456A—12/12/02 Stop 2 13

CL-141

Contextual Info: F A I R Ç H F100182 9-Bit Wallace Tree Adder I ^ A Schlumberger Company F100K ECL Product Connection Diagrams Description The F100182 is a 9-bit Wallace tree adder. It is designed to assist in performing high-speed hardware multi­ plication. The device is designed to add 9-bits of data

Contextual Info: II s’ !' “ '• '■<: ! I, ! Il W ' j T. I /. I 'j li U 's ! >J o S1 ll , I /V 's . P R E L IM IN A R Y Figure 1. Block Diagram FBIN 'J GA1088 R E F C LK SO F1 FO GND ni nri m m m m rr 11-Output TES T Configurable Clock Buffer VD D QO Features GND * Q1

Contextual Info: 165 CONNECTION DIAGRAM PINOUT A J4/74165 O ' O ' ^ ^ L S ^ L S IB S o to v t* ' 8-BIT PARALLEL-TO-SERIAL CONVERTER DESCRIPTION — The '165 is an 8-bit parallel load or serial-in register with complementary outputs available from thejast stage. Parallel inputing occurs

Contextual Info: r B t § tt / üf r S E M I C O N D U C T O R , I N C IQ # C O M P U T I N G AND NETWORKING Figure 1. Block Diagram CLKIN GA1210E FBIN Clock Doubler/ Two-Phase Generator Features TriQuint's GA1210E is a low-skew TTL-level clock doubler chip. It produces multiple clock

Contextual Info: PI6LC48P0401 4-Output LVPECL Networking Clock Generator Features Description ÎÎFour differential LVPECL output pairs The PI6LC48P0401 is a 4-output LVPECL synthesizer optimized to generate Ethernet reference clock frequencies and is a member of Pericom’s HiFlex family of high performance clock

7805 nec voltage regulator

Abstract: 7805 Packaged TO-3 block diagram of IC 7805 pin diagram of 7805 voltage regulator 7805 IC PIN DIAGRAM IN nec 7805 IC 7805 pin diagram
Contextual Info: PRELIMINARY DATA SHEET AGC AMPLIFIER UPC3211GR INTERNAL BLOCK DIAGRAM FEATURES • W IDE GAIN CONTROL RANGE: 55 dB TYP • LOW DISTORTION: IM3 = 57 dBc (TYP) at Pout = - 1 0 dBm IM 2 = 44 dBc (TYP) at P o u t = - 1 0 dBm • SUPPLY VOLTAGE: 9 V • PACKAGED IN 20 PIN SSOP SUITABLE FOR HIGHDENSITY SURFACE MOUNT

L band upconverter

Abstract: MMIC L band to Ku converter 8104g
Contextual Info: SILICON MMIC UPCONVERTER AND QUADRATURE MODULATOR FEATURES UPC8104GR FUNCTIONAL BLOCK DIAGRAM WIDE SUPPLY VOLTAGE RANGE: 2.7 ~ 5.5 V L02 BROADBAND OPERATION: RF out = 0.8 - 2.4 GHz MOD out = 100 - 400 MHz, l/Q = DC to 10 MHz INTERNAL 90° PHASE SHIFTER PORTS FOR EXTERNAL IF FILTER

FS23

Abstract: ICS91309I
Contextual Info: ICS91309I Integrated Circuit Systems, Inc. High Performance Communication Buffer General Description Features The ICS91309I is a high performance, low skew, low jitter zero delay buffer. It uses a phase lock loop PLL technology to align, in both phase and frequency, the REF

CQFP68

Abstract: 1 GSPS 2144a schematics ps satellite receiver 5962-0050401QYC JTS8388B TS81102G0 TS8388BF TS8388BFS TS8388BG
Contextual Info: Features • • • • • • • • • • • • • • • • • • • • • • • 8-bit Resolution ADC Gain Adjust 1.5 GHz Full Power Input Bandwidth -3 dB 1 GSPS (min) Sampling Rate SINAD = 44.3 dB (7.2 Effective Bits), SFDR = 58 dBc,

DIOD MARKING CODE f2

Contextual Info: Features • • • • • • • • • • • • • • • • • • • • • 8-bit Resolution ADC Gain Adjust 1.5 GHz Full Power Input Bandwidth -3 dB 1 GSPS (min) Sampling Rate SINAD = 44.3 dB (7.2 Effective Bits), SFDR = 58 dBc, at FS = 1 GSPS, FIN = 20 MHz

BDC 47 transistor

Abstract: JTS8388B RO4003 TS81102G0 TS8388BGL TSEV8388BGL
Contextual Info: Features • • • • • • • • • • • • • • • • • • • • 8-bit Resolution ADC Gain Adjust 1.8 GHz Full Power Input Bandwidth -3 dB 1 GSPS (min) Sampling Rate SFDR = 58 dBc, SINAD = 44.3 dB (7.2 Effective Bits), at FS = 1 GSPS, FIN = 20 MHz

SK1500

Abstract: SK1501 SK1502 SK1503 SK1504 SK1525 SK1526 SK1527 SK1528 SK15XX
Contextual Info: SK15XX Family 1:5 Signal Distribution PRELIMINARY HIGH-PERFORMANCE PRODUCTS SK15XX Family Functional Block Diagram OUT0 OUT0* IN IN* D Q D* Q* 1 CLK CLK* OUT1 OUT1* OUT2 OUT2* OUT3 OUT3* SEL* SEL OUT4 OUT4* Revision 1/ January 23, 2001 1 www.semtech.com SK15XX Family

SK1900

Abstract: SK1901 SK1902 SK1903 SK1904 SK1925 SK1926 SK1927 SK1928
Contextual Info: SK19XX Family 1:9 Signal Distribution HIGH-PERFORMANCE PRODUCTS PRELIMINARY SK19XX Family Functional Block Diagram OUT0 OUT0* OUT1 OUT1* OUT2 OUT2* OUT3 OUT3* IN IN* D Q D* Q* 1 CLK CLK* OUT4 OUT4* OUT5 OUT5* OUT6 OUT6* SEL* SEL OUT7 OUT7* OUT8 OUT8* Revision 1/January 23, 2001