POS Search Results

Contextual Info: 54AC11109, 74AC11109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET TI0066— D2957, M ARCH 1987— REVISED M ARCH 1990 Flow-Through Architecture to Optimize PCB Layout 54AC11109 . . . J PACKAGE 74AC11109 . . . D OR N PACKAGE TOP VIEW

SN74HC74

Contextual Info: SN54HC74, SN74HC74 DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET _ SCLS094A - DECEMBER 1982 - REVISED JANUARY 1996 Package Options Include Plastic Small-Outline D , Shrink Small-Outline (DB), Thin Shrink Small-Outline (PW), and

Contextual Info: SN5409, SN54LS09, SN54S09, SN7409, SN74LS09, SN74S09 QUADRUPLE 2-INPUT POSITIVE-AND GATES WITH OPEN-COLLECTOR OUTPUTS DECEMBER 1 9 8 3 -R E V IS E D M A R C H 1 9 8 8 Package Options Include Plastic "Sm all Outline" P ackages, Ceram ic Chip Carriers and Flat P ackages, and Plastic and Ceram ic

Contextual Info: 8 THIS DRAWING IS UNPUBLISHED. COPYRIGHT - 7 RELEASED FOR PUBLICATION BY TYCO ELECTRONIC5 CORPORATION. LOC ALL RIGHTS RESERVED. DIST REVISIONS AD 00 P LTR H 1 . ASSEMBLY MAY BE BROKEN TO THE DESIRED NUMBER OF POSITIONS 2. TRUE POSITION TOLERANCE OF THE POST TIPS APPLIES WHEN THE HEADER

Contextual Info: 54AC11032, 74AC11032 QUADRUPLE 2-INPUT POSITIVE-OR GATES TI0060— D2957, JULY 1987— REVISED MARCH 1990 54A C 11032 . . . J PACKAGE 74A C 11032 . . . D OR N PACKAGE • Flow-Through Architecture to Optimize PCB Layout TOP VIEW • Center-Pin V c c and GND Configurations to

sn 74 ls 11 020 n

Abstract: LS1020A LS102
Contextual Info: SN 54A LS1020A , S N 74 A LS 1 020 A DUAL 4-INPUT POSITIVE-NAND BUFFERS D2661, APRIL 1982-REVISED MAY 1986 • Buffer Version of 'A LS20B • Package Options Include Plastic "Sm all Outline" Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-m il

Contextual Info: 54AC11021,74AC11021 DUAL 4-INPUT POSITIVE-AND GATES _ D2957. JULY 1987 - REVISED APRIL 1993 54AC11021 . . . J PACKAGE 74AC11021 . . . D OR N PACKAGE TOP VIEW * Flow-Through Architecture Optimizes PCB Layout * Center-Pin Vcc and GND Configurations

Contextual Info: 54AC11002, 74AC11002 QUADRUPLE 2-INPUT POSITIVE-NOR GATES D2957, JUNE 1987 - REVISED APRIL 1993 54AC11002 . . . J PACKAGE 74AC11002 . . . D OR N PACKAGE TOP VIEW Flow-Through Architecture Optimizes PCB Layout Center-Pin Vcc and GND Configuration Minimizes High-Speed Switching Noise

IC SN74HC

Abstract: SN74HCTOO SN74HC
Contextual Info: SN54HCT00, SN74HCT00 QUADRUPLE 2-INPUT POSITIVE NANO GATES D 3 2 4 3 , NOVEMBER 1968 Inputs are TTL-Voftage Compatible S N 54H C T00 S N 74H C T00 Package Options Include Plastic "Small Outline" Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil

marking 3G

Contextual Info: TC4S01F TO SHIBA C MOS DIGITAL INTEGRATED C IR C U IT SILICO N M ONOLITHIC 2 INPUT NOR GATE Unit in mm + 0.2 23-0.3 The TC4S01F is 2-input positive logic NOR gates. + 0.2 Gate output w ith in v e rte r buffer im proves the 16 input-output ch arac te ristic s and if th e load

Contextual Info: TOSHIBA TC4S11F TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC TC4S11F 2 INPUT N A N D GATE The TC4S11F is 2-input positive logic NAND gates. Gate output with inverter buffer improve the inputoutput characteristics and even if the load capacitance

TLC32046

Contextual Info: TLC32046 WIDE-BAND ANALOG INTERFACE CIRCUITS Telecommunications Circuits See the TLC32046 Wide-Band Analog Interface Circuits Data Manual in Section 3 for product information. , Tex a s ^ In s t r u m e n t s POST OFFICE BOX 655303 * DALLAS, TEXAS 75265

74als1010

Abstract: 74ALS1010A 54als1010
Contextual Info: TYPES SN54ALS1010A, SN74ALS1010A TRIPLE 3-INPUT POSITIVE-NAND BUFFERS 0 2 6 6 1 , A P R IL 1 9 8 2 — R E V IS E D D E C E M B E R 1 9 8 3 Buffer Version o f 'A L S 1 0 SN 54 A LS 1 0 1 0 A . . . J PACKAGE Package O ptions Include Both Plastic and Ceram ic C h ip Carriers in Addition to Plastic

logic diagram of 7432

Abstract: Texas Instruments TTL 7432
Contextual Info: SN5432, SN 54LS32, SN54S32. SN7432, SN74LS32, SN74S32 QUADRUPLE 2-INPUT POSITIVE-OR GATES DECEMBER 1983-REVISED MARCH 1988 Package Options Include Plastic "Small Outline" Packages, Ceramic Chip Carriers and Flat Packages, and Plastic and Ceramic DIPs • SN 5432. SN 54LS32, SN 54S 32 . . . J OR W PACKAGE

Contextual Info: SN54LS15, SN54S15, SN74LS15, SN74S15 TRIPLE 3 INPUT POSITIVE AND GATES WITH OPEN-COLLECTOR OUTPUTS A P R IL 1 9 8 5 — R E V IS E D M A R C H Package Options Include Plastic "Sm all Outline" Packages, Ceramic Chip Carriers and Flat Packages, and Plastic and Ceramic

Contextual Info: SN54F20, SN74F20 DUAL 4-INPUT POSITIVE-NAND GATES D2932, MARCH 1987-REVISED JANUARY 1989 • Package Options Include Plastic "Small Outline" Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil DIPs S N 5 4 F 2 0 . . . J PACKAGE S N 7 4 F 2 0 . . . 0 OR N PACKAGE

Contextual Info: SN54HC132, SN74HC132 QUADRUPLE POSITIVE-NAND GATES WITH SCHMITT-TRIGGER INPUTS SCLS034B - DECEMBER 1982 - REVISED JANUARY 1996 • • • • • Operation From Very Slow Input Transitions Temperature-Compensated Threshold Levels High Noise Immunity Same Pinouts as ’HCOO

Contextual Info: 54ACT11002,74ACT11002 QUADRUPLE 2-INPUT POSITIVE-NOR GATES SCAS003A - D2957, JUNE 1987 - REVISED APRIL 1993 Inputs Are TTL-Voltage Compatible Flow-Through Architecture to Optimize PCB Layout Center-PIn V^c and GND Configurations Minimize High-Speed Switching Noise

TMPZ84C011

Abstract: TMPZ84C015BF6 TMPZ84C015BF-6 TMPZ84C011B TMPZ84C011BF-6 TMPZ84C011BF TMPZ84C011BF6 TMPZ84C015BF TMPZ84C810AF-6 TRD-100
Contextual Info: 8-Bit Microprocessor & Peripheral LSI TLCS-85 Family NMOS X44 Type No. Min. Inst. Execu­ tion time (ms) Function Max Supply Current (mA) Frequency (MHz) No. of Pins TMP8085AP-2 Microprocessor 0.8 170 5 40 ♦TMP8085AHP-2 Microprocessor 0.8 135 5 40 Notes) Postfix P: Plastic standard DIP (DIP), * : Supply voltage: 4.5-5.5V; Supply voltage: 4.75-5.25V, Operating temperature: 0~70”C

Contextual Info: SN54ALS11A, SN54AS11, SN74ALS11A, SN74AS11 TRIPLE 3-INPUT POSITIVE-AND GATES SDAS009C - MARCH 1984 - REVISED DECEMBER 1994 • Package Options Include Plastic Small-Outline D Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs

S1912

Abstract: las19u
Contextual Info: INTEGRATED CIRCU ITS U N IT R O D E 5 AMP POSITIVE VOLTAGE REGULATORS LAS 1900 SERIES FEATURES DESCRIPTION • Guaranteed Power Dissipation 50 Watts fa 80°C Case • Guaranteed input-output differential: - 2.6 Volts • Low noise, band gap reference • Remote sense capability

L78015

Contextual Info: TL780 SERIES POSITIVE VOLTAGE REGULATORS SLVS055B - APRIL 1981 - REVISED AUGUST 1995 • ±1% Output Tolerance at 25°C • +2% Output Tolerance Over Full Operating Range • Thermal Shutdown • Internal Short-Circuit Current Limiting • Pinout Identical to |jA7800 Series

Contextual Info: S IM 54ALS1 0 1 0A , SIM 74ALS1 □ 1 0 A TRIPLE 3 INPUT POSITIVE N A N D B U FFE R S D 2 6 6 1 , A P R IL 1 9 8 2 • Buffer Version of 'A LS 10A • Package Outline” Addition Ceramic S N 74A LS 1010A . . . D O R N • -R E V IS E D M A Y 1 9 8 6 S N 5 4 A L S 1 0 1 0 A . . . J PACKAGE

TL0100

Contextual Info: TOSHIBA T L D 1002 TOSHIBA LED LAMP TLG1002, TLGD1002, TLPG1002, TL01002 TLOE1002, TLY1002, TLYE1002, TLS1002 TLUR1002, TLRA1002, TLR1002 LED SURFACE MOUNT DEVICE U n it in m m LED CHIP POSITION a : TLRA1002, TLUR1002 b : O THER TYPE 2.0 L X1.25 (W )X1.1 (H) m m Size