PLXO Search Results

Contextual Info: 4 .7JV> AT&T Data Sheet T1 DS-1 and CEPT-1 Frequency Translator: PLXO Features • Translates from: —CEPT-1 x 2 (4.096 MHz) to DS-1 (1.544 MHz) —CEPT-1 x 2 (4.096 MHz) to DS-1C (3.152 MHz) —DS-1 (1.544 MHz) to CEPT-1 x 2 (4.096 MHz) —DS-1 C (3.152 MHz) to CEPT-1 x 2 (4.096 MHz)

design DRO

Abstract: dro 10 ghz Pldro
Contextual Info: LOW NOISE PHASE LOCKED DRO 37 SPECIAL FEATURES This PLDRO uses two phase lock loops for good phase noise performance. The 6.6 GHz DRO, which drives the far-out noise levels, is phase locked to an internal 110 MHz PLXO, which drives the moderately close-in

M28754

Abstract: TRANSISTOR S 813 plxo M28754/36-04
Contextual Info: MULTI-OUTPUT PLXO ASSEMBLY 23 • Five Frequency-Coherent Outputs • Low Phase Noise: - 132 dBc/Hz @ 100 kHz offset • Low Spurious: ≤ - 80 dBc • Fast Switching: 300 nsec • Multiple Built-In-Test Points Using two phase locked, AT-Cut crystal oscillators

Contextual Info: Frequency Range P.5 9 « 8 !M & K -K Simple Packaged Crystal Oscillator/CXO Temperature Compensated Crystal Oscillator/TCXO. VC-TCXO £S*Mt£i?kaie££ Temperature Compensated Crystal Oscillator with Voltage Controlled Function/VCXO HE$Jffl3!7kS£ig£ Oven Controlled Crystal Oscillator/OCXO

CB4CLE

Abstract: cb4re CB8CLED cb8cle CB4CLED X74-160 x4202 CB16CE sr4cled 2 bit magnitude comparator using 2 xor gates
Contextual Info: ON LIN E R LIBRARIES G UI DE T ABL E OF CONT ENT S INDEX GO T O OT HER BOOKS 0 4 0 1410 Copyright 1993-1995 Xilinx Inc. All Rights Reserved. Contents Chapter 1 Xilinx Unified Libraries Overview .

FDS 4468

Abstract: HBT 01 - 04G INTEL 486 sx sl pinout 240950 JVC 4580 fds 4418 TOT - 4301 INTEL DX4 241199 Intel DX4TM
Contextual Info: intj, INTEL486 PROCESSOR FAMILY • Write-Back Enhanced lntelDX4™ Processor — Up to 100-MHz Operation — Speed-Multiplying Technology — 32-Bit Architecture — 16K-Byte On-Chip Write-Back Cache — Integrated Floating-Point Unit — 3.3V Core Operation with 5V Tolerant

IC Reader DLL Function Library Reference Manual

Abstract: small doorbell project i960HA INT960 INTS9080 PCI9080 PLX9080 RDKF
Contextual Info: PCI SDK Programmer’s Reference Manual Release 1.2, initial publishing December 11, 1997. Copyright 1997, PLX Technology, Inc. All rights reserved. This document contains proprietary and confidential information of PLX Technology Inc. PLX . The contents of this document may not be copied nor duplicated in any form, in whole or in part,

tcxo 139.264 mhz

Contextual Info: Frequency Control Products Catalog Definitions APR A bsolute Pull Range. The m axim um input signal variation that can be received or tracked by a VCXO, VCSO or Timing Recovery Device. A clock signal or data stream w ith a stability of ± 32 ppm, which is to be retimed or synchronized to, requires a VCXO, VCSO or Timing Recovery

42XS-3

Contextual Info: fax id: 5410 CY7C4425/4205/4215 _ CY7C4225/4235/4245 "64, 256, 512, 1K, 2K, 4K x 18 Synchronous FIFOs Features controlled by a free-running clock WCLK and a write enable pin (WEN). • High-speed, iow-power, first-in first-out (FIFO) memories

Contextual Info: S X P.5 Frequency Range w & 'a m m & .- m Simple Packaged Crystal Oscillator/CXO Temperature Compensated Crystal Oscillator/TCXO. VC-TCXO P7 P 25 SJg««3!7.ki8fgJji3g

ATT2C12

Abstract: OA50 diodes
Contextual Info: Data Sheet March 1995 AT&T Microelectronics Optimized Reconfigurable Cell Array ORCA 2C Series Field-Programmable Gate Arrays Features Description • High-performance, cost-effective 0.5 firm technology (four-input look-up table delay less than 3.6 ns)

ATT ORCA fpga

Abstract: LSR 2C12
Contextual Info: Data Sheet April 1995 ^A T& T Microelectronics Optimized Reconfigurable Cell Array ORCA 2C Series Field-Programmable Gate Arrays Features Description • High-performance, cost-effective 0.5 pm technology (four-inplit look-up table delay less than 3.6 ns)

9636L

Abstract: GHOST CHIP LF
Contextual Info: DAC0630/DAC0631 g n National Æjâ Semiconductor DAC0630/DAC0631 Triple 6-Bit Video DAC with Color Palette General Description Features The DAC0630 and DAC0631 are monolithic triple 6 -bit video digital-to-analog converters with on-chip 256 x 18 bit color

ks 4290 industrial controller

Abstract: AKA NF 028 ATT2C12 ATT ORCA fpga ATT2C08 ATT2C15 52833 trw 2015 ptc ei 8n CODE PJ 62-00
Contextual Info: Preliminary Data Sheet January 1995 AT&T Microelectronics Optimized Reconfigurable Cell Array ORCA 2C Series Field-Programmable Gate Arrays Features • High density: 3,500 to 26,000 usable gates ■ High I/O: up to 384 usable I/O ■ High-performance 0.5 (xm CMOS technology