PLD DECODER Search Results

100 PIN tQFP ALTERA DIMENSION

Abstract: epm7128stc100 84 pin plcc lattice dimension TQFP 144 PACKAGE footprint 256-pin Plastic BGA 17 x 17 epm7192 footprint tqfp 208 PLMQ7192/256-160NC SVF pcf EPF10K100B
Contextual Info: Newsletter for Altera Customers ◆ Third Quarter ◆ August 1998 Raphael: Embedded PLD Family for System-Level Integration The new RaphaelTM programmable logic device PLD family, based on the revolutionary MultiCoreTM architecture, meets system-level design challenges by

Contextual Info: Lattice icorporatfont0r ispLSI' 2064E In-System Programmable SuperFAST High Density PLD Features Functional Block Diagram • SuperFAST HIGH DENSITY IN-SYSTEM PROGRAMMABLE LOGIC — 2000 PLD Gates — 64 I/O Pins, Four Dedicated Inputs — 64 Registers

isplsi2

Contextual Info: Lattice ;Semiconductor I Corporation ispLSI 2032E In-System Programmable SuperFAST High Density PLD Features Functional Block Diagram SuperFAST HIGH DENSITY IN-SYSTEM PROGRAMMABLE LOGIC — 1000 PLD Gates — 32 I/O Pins, Two Dedicated Inputs — 32 Registers

Contextual Info: Lattice ; Semiconductor •Corporation ispLSI' 2032VE 3.3V In-System Programmable High Density SuperFAST PLD Features Functional Block Diagram SuperFAST HIGH DENSITY IN-SYSTEM PROGRAMMABLE LOGIC — — — — — 1000 PLD Gates 32 I/O Pins, Two Dedicated Inputs

Contextual Info: Lattice ; ; ; ; Semiconductor •• ■■ Corporation ispLSI 2032VL * VANTI S 2.5V In-System Programmable SuperFAST High Density PLD Functional Block Diagram Features SuperFAST HIGH DENSITY IN-SYSTEM PROGRAMMABLE LOGIC — — — — — 1000 PLD Gates

Contextual Info: Latticc ispLSr3448 ; ; ; Semiconductor •■■ Corporation In-System Programmable High Density PLD Functional Block Diagram Features • HIGH-DENSITY PROGRAMMABLE LOGIC — 224 I/O — 20000 PLD Gates — 672 Registers — High Speed Global Interconnect

Contextual Info: Lattice' | Semiconductor I Corporation ispLSI 2032E In-System Programmable SuperFAST High Density PLD Functional Block Diagram Features • SuperFAST HIGH DENSITY IN-SYSTEM PROGRAMMABLE LOGIC — 1000 PLD Gates — 32 I/O Pins, Two Dedicated Inputs — 32 Registers

ispLS11048

Abstract: 548-5N
Contextual Info: Lattice ispLSI 1048 ;Semiconductor I Corporation In-System Programmable High Density PLD Features Functional Block Diagram HIGH-DENSITY PROGRAMMABLE LOGIC — 8000 PLD Gates — 96 I/O Pins, Ten Dedicated Inputs — 288 Registers — High-Speed Global Interconnects

6402 uart

Abstract: digital serial data filtering using fir filters megafunction
Contextual Info: Introduction to Target Applications February 1997, ver. 1 With programmable logic device PLD densities reaching 250,000 gates, it is now possible to implement entire digital subsystems within a single PLD. This new level in density creates greater opportunities for designers

lattice 1016-60LJ

Abstract: ispls11016 ispLSI1016 til 701 1016-60 Lattice 1016-80LJ 1016-80LJ loadable counter with timing diagram
Contextual Info: Latticc ispLSI 1016 ; ; ; Semiconductor •■■ Corporation In-System Programmable High Density PLD Functional Block Diagram Features • HIGH-DENSITY PROGRAMMABLE LOGIC — High-Speed Global Interconnect — 2000 PLD Gates — 32 I/O Pins, Four Dedicated Inputs

1032-60LJ

Abstract: 1032-60LJI 1032-60LTI 1032-90LJ 1032-90LT smd JSs 13 smd JSs 24
Contextual Info: Lattice ispLSI 1032 I Semiconductor I Corporation In-System Programmable High Density PLD Functional Block Diagram Features HIGH-DENSITY PROGRAMMABLE LOGIC — High Speed Global Interconnect — 6000 PLD Gates — 64 I/O Pins, Eight Dedicated Inputs — 192 Registers

Contextual Info: Latti C6 ' Semiconductor ¡Corporation ispLSI 1032E _ In-System Programmable High Density PLD Features Functional Block Diagram • HIGH DENSITY PROGRAMMABLE LOGIC — 6000 PLD Gates — 64 I/O Pins, Eight Dedicated Inputs — 192 Registers — High Speed Global Interconnect

isplsi2

Abstract: ISP2064 isplsi2064
Contextual Info: Lattice I Semiconductor I Corporation ispLSI 2064E In-System Programmable SuperFAST High Density PLD Features Functional Block Diagram SuperFAST HIGH DENSITY IN-SYSTEM PROGRAMMABLE LOGIC — 2000 PLD Gates — 64 I/O Pins, Four Dedicated Inputs — 64 Registers

Contextual Info: Lattice' ispLSI 1024 | Semiconductor I Corporation In-System Programmable High Density PLD Functional Block Diagram Features HIGH-DENSITY PROGRAMMABLE LOGIC — High-Speed Global Interconnect — 4000 PLD Gates — 48 I/O Pins, Six Dedicated Inputs — 144 Registers

VOGT 503

Abstract: vogt 503 20 VOGT 503 10 vogt b6 vogt b3 vogt a5 vogt b7 vogt 503 20 999 vogt a3 VOGT RO 503
Contextual Info: Lattica ;Semiconductor I Corporation ispLSI 1016 In-System Programmable High Density PLD Functional Block Diagram Features HIGH-DENSITY PROGRAMMABLE LOGIC — High-Speed Global Interconnect — 2000 PLD Gates — 32 I/O Pins, Four Dedicated Inputs — 96 Registers

M6038

Contextual Info: Lattica !Semiconductor I Corporation ispLSI 1032 In-System Programmable High Density PLD Features Functional Block Diagram • HIGH-DENSITY PROGRAMMABLE LOGIC — High Speed Global Interconnect — 6000 PLD Gates — 64 I/O Pins, Eight Dedicated Inputs — 192 Registers

Contextual Info: Lattice ;Semiconductor I Corporation ispLSI 2096VE 3.3V In-System Programmable SuperFAST High Density PLD Functional Block Diagram Features SuperFAST HIGH DENSITY PROGRAMMABLE LOGIC — 4000 PLD Gates — 96 I/O Pins, Six Dedicated Inputs — 96 Registers

2032E

Abstract: 2032VE
Contextual Info: ispLSI 2032E/2032VE In-System Programmable SuperFAST High Density PLD • SuperFAST HIGH DENSITY ISP LOGIC 1000 PLD Gates 32 I/O Pins, Two Dedicated Inputs 32 Registers High Speed Global Interconnect Wide Input Gating for Fast Counters, State Machines,

Contextual Info: Lattice \ Corporatk^nt0r ispLSr 5512V In-System Programmable 3.3V SuperWIDE High Density PLD Features Functional B lock Diagram SuperWIDE HIGH DENSITY IN-SYSTEM PROGRAMMABLE LOGIC — 3.3V Power Supply — User Selectable 3.3V/2.5V I/O — 24000 PLD Gates / 512 Macrocells

Contextual Info: Lattica I Semiconductor I Corporation ispLSI 2096VE 3.3V In-System Programmable SuperFAST High Density PLD Functional Block Diagram Features SuperFAST HIGH DENSITY PROGRAMMABLE LOGIC — 4000 PLD Gates — 96 I/O Pins, Six Dedicated Inputs — 96 Registers

Contextual Info: Lattice ; ; ; ; Semiconductor •• ■■ Corporation ispLSI 2096VL * VANTI S 2.5V In-System Programmable SuperFAST High Density PLD Functional Block Diagram Features SuperFAST HIGH DENSITY PROGRAMMABLE LOGIC — 4000 PLD Gates — 96 I/O Pins, Six Dedicated Inputs

Contextual Info: Lattice j Corporatfonît0r ispLSI 2128E In-System Programmable SuperFAST High Density PLD Features Functional Block Diagram • SUPERFAST HIGH DENSITY IN-SYSTEM PROGRAMMABLE LOGIC — 6000 PLD Gates — 128 I/O Pins, Eight Dedicated Inputs — 128 Registers

Contextual Info: ispLSI 2064E In-System Programmable SuperFAST High Density PLD Features Functional Block Diagram • SuperFAST HIGH DENSITY IN-SYSTEM PROGRAMMABLE LOGIC — 2000 PLD Gates — 64 I/O Pins, Four Dedicated Inputs — 64 Registers — High Speed Global Interconnect

2096VE

Contextual Info: ispLSI 2192VL 2.5V In-System Programmable SuperFAST High Density PLD Functional Block Diagram — — — — — 8000 PLD Gates 96 I/O Pins, Nine Dedicated Inputs 192 Registers High Speed Global Interconnect Wide Input Gating for Fast Counters, State