PLCC 44 INTEL PACKAGE DIMENSIONS Search Results

AN82527F8

Abstract: intel 82527 EN210 82527 IA82527 IA82527-PLC44A IA82527-PLC44A-R IA82527-PTQ44A InnovASIC AN82527
Contextual Info: 04 May 2007 IA82527 CAN Serial Communications Controller As of Production Ver. 00 PRELIMINARY IA82527 Serial Communications Controller ▪ CAN Protocol Data Sheet Document Version 1.0 Copyright  2007 EN21070504-00 Page 1 of 45 www.Innovasic.com Customer Support:

Contextual Info: l p 13« PIMMMGT [PIF3EWEW in te l. 80L188EA8 16-BIT HIGH INTEGRATION EMBEDDED PROCESSOR • 3V Operation, Vcc = 2.7V-5.5V ■ Full Static Operation ■ True CMOS Inputs and Outputs Integrated Feature Set — Static 186 CPU Core — Power Save, Idle and Powerdown

SAE AMS-QQ-N-290

Abstract: PLCC 32 SOCKET pinout
Contextual Info: P/N 1111163 40-Pin DIP-to-Socketable PLCC Adapter FEATURES • Can be used with Intel 80/83C652 and 80C251 microprocessors and any IC that follows standard DIP-to-PLCC pinout conventions. • Allows user to switch package styles and avoid shortage problems.

motorola t3 switch

Abstract: CML65 IC2 Bus Addresses Transistor t30 motorola SI15 Mini8
Contextual Info: NW1507 Multi-Rate Time Division Switch Matrix Preliminary, May 2000 Ver1.1

EXAR ST16C654

Contextual Info: ST16C554/554D 2.97V TO 5.5V QUAD UART WITH 16-BYTE FIFO JUNE 2006 REV. 4.0.1 GENERAL DESCRIPTION FEATURES The ST16C554/554D 554 is a quad Universal Asynchronous Receiver and Transmitter (UART) with 16 bytes of transmit and receive FIFOs, selectable receive FIFO trigger levels and data rates of up to 1.5

Contextual Info: in te i 80L188EA-13, -8 16-BIT HIGH INTEGRATION EMBEDDED PROCESSOR • 3V O p e ra tio n , V c c = 2 .7 V -5 .5 V ■ F u ll S ta tic O p e ra tio n ■ T ru e C M O S In p u ts a n d O u tp u ts ■ Integrated Feature Set — Static 186 CPU Core — Power Save, Idle and Powerdown

80960SA

Abstract: 80960SB 65A176 AD427
Contextual Info: 80960SA EMBEDDED 32-BIT MICROPROCESSOR WITH 16-BIT BURST DATA BUS • High-Performance Embedded ■ Pin Compatible with 80960SB Architecture — 20 MIPS* Burst Execution at 20 MHz — 7.5 MIPS Sustained Execution at 20 MHz ■ 512-Byte On-Chip Instruction Cache

SC16C554B

Abstract: XR16V554IV 16-BYTE 16C550 ST16C454 ST16C554 TL16C554A XR16V554 d7522 RXB38
Contextual Info: XR16V554/554D 2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO MAY 2007 REV. 1.0.1 GENERAL DESCRIPTION FEATURES • Pin-to-pin compatible with ST16C454, ST16C554, The XR16V554 V554 is a quad Universal Asynchronous Receiver and Transmitter (UART) with 16 bytes of transmit and receive FIFOs, selectable

Contextual Info: XR16V554/554D PRELIMINARY 2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO SEPTEMBER 2006 REV. P1.0.2 GENERAL DESCRIPTION FEATURES • Pin-to-pin compatible with ST16C454, ST16C554, The XR16V554 V554 is a quad Universal Asynchronous Receiver and Transmitter (UART) with

LXT360PE

Abstract: LXT361PE LXT360LE LXT360 LXT360NE LXT360QE LXT361 LXT361NE LXT361QE coax a61
Contextual Info: DATA SHEET AUGUST 1998 Revision 3.0 LXT360/361 Integrated T1/E1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications General Description The LXT360 and LXT361 are the first full-featured, fully integrated, combination transceivers for E1 ISDN Primary Rate Interface and T1 long and short haul applications.

valor lt6003

Contextual Info: inUI 82503 DUAL SERIAL TRANSCEIVER DST 82503 PRODUCT FEATURE SET OVERVIEW • Single Component Ethernet* Interface to Both 802.3 10BASE-T and AUI ■ Diagnostic Loopback ■ Reset, Low Power Modes ■ Automatic or Manual Port Selection ■ Network Status Indicators

Contextual Info: in te i 80960SA EMBEDDED 32-BIT MICROPROCESSOR WITH 16-BIT BURST DATA BUS • High-Performance Embedded Architecture — 20 MIPS* Burst Execution at 20 MHz — 7.5 MIPS Sustained Execution at 20 MHz ■ 512-Byte On-Chip Instruction Cache — Direct Mapped

Contextual Info: Ä IQ W Ä G O O S 0 M [F K M 1 Ä ¥ D ® K 1 in te l 80C186EA20,16,12 16-BIT HIGH INTEGRATION EMBEDDED PROCESSOR • 80C186 Upgrade for Power Critical Applications ■ Full Static Operation ■ True CMOS Inputs and Outputs Direct Addressing Capability to

ST16C454

Abstract: ST16C554 TL16C754B V654 XR16V654 XR16V654IV efr 135
Contextual Info: XR16V654/654D 2.25V TO 3.6V QUAD UART WITH 64-BYTE FIFO MAY 2007 REV. 1.0.1 GENERAL DESCRIPTION FEATURES • Pin-to-pin compatible with ST16C454, ST16C554, The XR16V6541 V654 is an enhanced quad Universal Asynchronous Receiver and Transmitter (UART) each with 64 bytes of transmit and receive

Contextual Info: NOV 3 t Î99I ! Preliminary Advanced Micro Devices Am2075 ISDN Digital Exchange Controller IDEC DISTINCTIVE CHARACTERISTICS • Four independent HDLC channels ■ 64-byte FIFO storage per channel and Programmable time slots and channel data rates (up to 4 Mb/s)

intel 8096

Abstract: 8096 pin diagram intel 8096 instruction set SC11011CV 8250 uart intel 8096 instruction set 8096 processor architecture 8250 intel uart 8250b 8096 instruction
Contextual Info: PRELIMINARY r A I /l il lY ll l ìA A l O SIERRA SEMICONDUCTOR X°EmA 8 N W SC11009/SC11010/SC11011 2400 BPS M odem Advanced Coprocessor MAC • Direct interface to SCI 1006 single chip modem. • Complete “A T” command set in firmware • Built-in UART.

fo535

Abstract: gruner RELAY 704 150S5 C1370 MT8930BE RESO 12 - 0160 RELAY gruner 740 FC40P gruner 704 RELAY
Contextual Info: « - „ p MT8930B Subscriber N etw ork Interface Circuit . * CMOS ST-BUS FAMILY Preliminary Info rm ation 9161-002-170-NA Features ISSUE 2 August 1993 Ordering Information CCITT 1.430 and ANSI T1.605 S/T interface Full-duplex 2B + D , 192 kbit/s transmission

3AD5

Contextual Info: in te i 80C188EB-16, -13, -8 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSOR • Full Static Operation • True CMOS Inputs and Outputs • - 40°C to + 85°C Operating Tem perature Range • Low System Cost 8-Bit Interface • Integrated Feature Set — Low -Power Static CPU Core

Contextual Info: Full Duplex LSI LOGIC 80C25 AutoDUPLEX CMOS Ethernet Interface Adapter in 28L Package 96345 This document is an LSI Logic document. Any reference to SEEQ Technology should be considered LSI Logic. Note: Check for latest Data Sheet revision before starting any designs.

Contextual Info: in te i JAN 3 ölMföRfflÄTTO «] 80C287A CHMOS III MATH COPROCESSOR High Performance 80-Bit Internal Architecture Implements ANSI/IEEE Standard 7541985 for Binary Floating-Point Arithmetic Implements Extended 80387 Instruction Set Directly Extends CPU’s Instruction Set

Crystal CS492604

Abstract: CS4926 read/outboard cdi circuit diagram dolby bass CRD4923 CS4226 CS4925 CS4927 CS4928 CS4929
Contextual Info: CS4923/4/5/6/7/8/9 Multi-Channel Digital Audio Decoders l CS4923/4/5/6/7/8 Description features — Optional Virtual 3D Output — Simulated Surround and Programmable Effects — Real Time Autodetection of Dolby Digital , DTS®, MPEG Multi-Channel and PCM

g796

Abstract: MT9076AP GR-303-CORE G964 mitel e1/t1 MT9076 MT90823 MT90221 MT9076AB PUB43801
Contextual Info: MT9076 T1/E1/J1 3.3V Single Chip Transceiver Product Brief Features • The MT9076 is a highly featured single chip solution for terminating T1/E1/J1 trunks. It contains a longhaul LIU, an advanced framer, a high performance PLL, and 3 HDLCs. In T1 mode, the MT9076 supports D4, ESF and

WJ972MA4

Abstract: B3814-02 LXT971A line code MLT b347 10BT LXT972M 302875 line code MLT-3 "network interface cards"
Contextual Info: Intel LXT972M Single-Port 10/100 Mbps PHY Transceiver Datasheet The Intel® LXT972M Single-Port 10/100 Mbps PHY Transceiver is an IEEE compliant Fast Ethernet PHY Transceiver that directly supports both 100BASE-TX and 10BASE-T applications. It provides a Media Independent Interface MII for easy attachment to 10/100 Media Access

Contextual Info: April 1997 Micro Linear ML2652/ML2653 10Base-T Physical Interface Chip GENERAL DESCRIPTION FEATURES The ML2652, 10BASE-T Physical Interface Chip, is a complete physical interface for twisted pair and AUI Ethernet applications. It combines a 10BASE-T MAU, Manchester Encoder/Decoder, and Twisted Pair Interface